LMK04806: LMK04806 Set up?

Hello Henry,

It is possible.  However you should use a VCXO frequency that is related better to 2457.6 MHz so that PLL2 will operate with a higher phase detector frequency.  This will allow the LMK04806 operate more 'efficiently' with less PLL noise.  Using a VCXO of even 12.288 MHz would allow you to operate with 24.576 MHz phase detector frequency after using the doubler.  I might suggest a 122.88 MHz for best performance.  I typically consider >= 100 MHz for best performance.

As for PLL1, I typically choose a phase detector frequency of around 1 MHz.  Also, I'd try using a higher charge pump current like 400 uA.  In general, pick a charge pump current as high as you can without the loop filter capacitors becoming too large given the loop bandwidth you want to achieve for jitter cleaning.  If the phase detector frequency is low enough lets say < 50 to 100 kHz, the charge pump gain is low enough (like 100 uA), and the VCXO input leakage is high enough (input impedance ~100 kohm).  You may find the PLL1 DLD won't assert because the PLL1 CP will be turned on so much to stay in lock that it will be tricked into thinking it's out of lock.

Please also see my e2e document on choosing loop bandwidths, e2e.ti.com/.../664163.aspx

FOr your outputs, consider grouping the 245.76 MHz together to help avoid spurs by frequency planning.  Meaning putting the same frequencies together as much as possible to avoid direct crosstalk.  You have a lot of different frequencies, so you will be limited in what you can do, but... for frequency planning recommendations, I consider CLKout2/3/4/5 to be the most isolated,  CLKout0/1/10/11 the second most isolated, and finally CLKout6/7/8/9 least isolated.

73,
Timothy