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LMX2594EVM: Lock Time in "full assist" mode does not match to simulation

porat yifrah
Prodigy 150 points
Part Number: LMX2594EVM


Hi,

I am using in LMX2594EVM  to synthesize frequencies from 4GHz to 8GHz. 

(for the question-  F_satrt = 4200Mhz  F_final = 4310MHz)

To improve the lock time of the PLL i chose to work with "full assist" mode.

1.  I found the VCO core (VCO_SEL) (to 4310 MHZ)
2.  I found the VCO band (VCO_CAPCTRL) (to 4310 MHZ)
3.  I found the VCO amplitude (VCO_DACISET), (to 4310 MHZ)

Everything works fine, and there is a change for the better in "lock time" between full assist to FCAL_EN.

But it is not suitable for simulation!

According to PLLatinum i need to get 219.8 us lock time but in LAB i got ~450 us ! (~X2) ( there are other frequencies that i got ~350 us)

SEE ATTACED

 Plase  advise.

Environment:

Fout: 4200MHz ---> 4310MHz

Oscillator: 100M - external 

Loop filter - C1 :2.2nf , C2 - 100nf , C3 - 1.5nf , R2- 270 , R3 - 330

Kpd (CP) - 15mA

Loop Bandwidth= 15 KHz

Phase Margin = 60 deg

Fpd = 2.5MHz

Thanks,

Porat. 

reportTI.pptx

  • 0
    TI__Mastermind 28021 points
    Porat,

    The lock time consists of two parts:
    1. VCO Calibration Time
    2. Analog lock time.

    Now for the VCO calibration time, I suspect that what is going on is that you are writing too slow. For instance, suppose you first change the PLL_N divider. If there is too much wait before the next write, then the VCO tuning voltage will slam into the rail and increase the lock time to longer than the simulation says as the simulation does not model this effect.

    Regards,
    Dean
  • 0 in reply to Dean Banerjee
    TI__Mastermind 28021 points
    One more thing, I didn't see the attachment. I looked at slide 8 and it seems that there is a long "tail". Sometimes this can be due to dielectric absorption of the capacitors. In other words, you might try changing the capacitors to NP0/COG/FILM if not already, especially capacitor C2.

    Regards,
    Dean