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CDCLVP1102: How to use CDCLVP1102 for LVDS input

Shyam Daram
Expert 1305 points

Part Number: CDCLVP1102
Other Parts Discussed in Thread: LMK03806, LMK04133

Hi,

I have a image sensor which requires a differential clock of 400Mhz

the clock to the sensor comes from a different fpga board which is connected through a 5 inch flex cable

so i want to use a clock buffer CDCLVP1102 before sensor clock input as the high speed clock coming through connector may become jittered

kindly help in how to connect LVDS clock through this buffer, is this a right choice, is there any low power variant of same ?

1. can make VCC 3.3v  ? or it should 2.5 V ?

2. what to do with AC_REF pin ? can i just leave it unconnected as its only required for LVPECL

3. should i have to put a 100 ohm termination at both input and output of CDCLVP1102 ?

4. there are two output for buffer can i ignore the other (OUTP[1] and OUTN[1]) which are unused ?

  • 0
    TI__Genius 9920 points
    Hi Shyam,
    A buffer can works as a redriver to terminate reflection caused by connector, but it can't reduce jitter. A buffer would add some additive jitter. Fortunately, CDCLVP1102 is a very low Additive Jitter: <100 fs, RMS in 10-kHz to 20-MHz offset range. If the image sensor need a LVPECL clock, CDCLVP1102 is the right choice.
    1, Either VC 3.3V or VCC 2.5V can work.
    2, Pin VAC_REF can be floated. Suggest to adopt datasheet "Figure 7. AC-Coupled Differential Input to Device". There are external bias resistors, which also works an equivalent differential 100 Ohm load .
    3,For output LVPECL, refer to datasheet "Figure 12. LVPECL Output DC and AC Termination for VCC = 2.5 V" and "Figure 13. LVPECL Output DC and AC Termination for VCC = 3.3 V".
    4, Unused output pair can be left floating.

    If it is too noisy for FPGA clock through flex cable an connectors, image sensor can't work normally, then we have to use a PLL based clock generator or jitter cleaner, for example, LMK03806, LMK04133 etc.

    Regards,
    Shawn
  • 0 in reply to Shawn Han
    Expert 1305 points

    Thanks for your detailed reply,

    i dont have any LVPECL signals

    the clock is an LVDS output from FPGA to Sensor, not other way

    so for above case i wish to connect buffer in between sensor and input connector on my image sensor card

    from your answer i would like to go ahead with below configuration

    1. VCC is 3.3v (only this is available for me)

    2. Pin VAC_REF shall be floated as i use LVDS only

    3. i am unclear about your explanation on adding a parallel 100 ohm termination for LVDS, from fig 6 of datasheet i understand, i require a 100 ohm parallel termination at input of CDCLVP1102 , any ways i shall be having one more 100 ohm parallel termination between terminal at the sensor end also.

    4. Un Used output pair shall be floating

    Kindly confirm above configuration

  • 0 in reply to Shyam Daram
    TI__Genius 9920 points
    Only one 100 Ohm termination for LVDS connection is needed, near receiver side (CDCLVP1102 input pins).
    Figure 6 is DC coupling LVDS mode, Figure 7 is AC coupling Differential signal mode (including LVDS).
    Figure 6 uses a parallel 100 Ohm. Figure 7 uses 82//130 = 50 Ohm on each line.
    Either coupling mode can be used for your case.
    If Sensor power supply is different than CDCLVP1102 power supply, or sensor is located in another board with a cable or a connector connected, considering sensor failure status and hot insertion, it is more safe to use AC coupling mode. That's why I recommended Figure 7.

    If you use both a source 100 Ohm termination near sensor driver and a receiver 100 Ohm termination near CDCLVP1102 input side, then the amplitude would be reduced to half than normal. It is no necessary in your case.