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CDCI6214: Please help to generate register datafor clock setting

Thomas Chang15933
Expert 4770 points

Part Number: CDCI6214

Dear Team:

 Customer design : input Xtal 25MHz,

CDCI6214 Y1 clock output :54MHz

                   Y2 clockoutput:25MHz

                   Y clock output:50MHz

COuld you help to generate the register setting?

Attached file is their right now register setting, but failed.

PLL   RegAddr    Data
       0001h     6882h
       0002h     0053h
       0003h     0000h
       0004h     0055h
       0005h     0028h
       0006h     19CAh
       0007h     040Ch
       0008h     0001h
       0009h     0000h
       000Ah     0000h
       000Bh     0000h
       000Ch     0000h
       000Dh     0000h
       000Eh     0000h
       000Fh     A037h
       0010h     921Fh
       0011h     26C4h
       0012h     FFFFh
       0013h     0000h
       0014h     0001h
       0015h     0000h
       0016h     0000h
       0017h     0595h
       0018h     0601h
       0019h     0406h
       001Ah     0718h
       001Bh     0000h
       001Ch     0000h
       001Dh     400Ah
       001Eh     5140h
       001Fh     1E72h
       0020h     0000h
       0021h     0007h
       0022h     0050h
       0023h     8000h
       0024h     0000h
       0025h     0004h
       0026h     0405h
       0027h     0A65h
       0028h     0008h
       0029h     8000h
       002Ah     0000h
       002Bh     0004h
       002Ch     0405h
       002Dh     0A65h
       002Eh     0008h
       002Fh     8000h
       0030h     0000h
       0031h     0004h
       0032h     0405h
       0033h     0A65h
       0034h     0008h
       0035h     8000h
       0036h     0000h
       0037h     0004h
       0038h     0405h
       0039h     0A65h
       003Ah     0008h
       003Bh     0009h
       003Ch     0010h
       003Dh     1000h
       003Eh     4210h
       003Fh     0210h

  • 0
    TI__Genius 16845 points

    Please see attached

    Kind regards,
    Lane

    Fullscreen ref-25MHz y1-54Mhz y2-50MHz y3-25MHz.txt Download 
    R70	0x00460000
R69	0x00450000
R68	0x00440000
R67	0x00430020
R66	0x00420000
R65	0x00410F34
R64	0x0040000D
R63	0x003F0210
R62	0x003E4209
R61	0x003D1500
R60	0x003C0018
R59	0x003B1069
R58	0x003A0008
R57	0x00390A65
R56	0x00380405
R55	0x00370000
R54	0x00360000
R53	0x00358000
R52	0x00340008
R51	0x00330A65
R50	0x00320405
R49	0x00310012
R48	0x00300000
R47	0x002F8000
R46	0x002E0008
R45	0x002D0A65
R44	0x002C0405
R43	0x002B0009
R42	0x002A0000
R41	0x00298000
R40	0x00280008
R39	0x00270A65
R38	0x00260405
R37	0x0025400A
R36	0x00240142
R35	0x002364BD
R34	0x00220050
R33	0x00210007
R32	0x00200000
R31	0x001F1E72
R30	0x001E5146
R29	0x001D421C
R28	0x001C0000
R27	0x001B0019
R26	0x001A0718
R25	0x00190000
R24	0x00180001
R23	0x00170000
R22	0x00160000
R21	0x00150000
R20	0x00140000
R19	0x00130000
R18	0x00120000
R17	0x001126C4
R16	0x0010921F
R15	0x000FA037
R14	0x000E0000
R13	0x000D0000
R12	0x000C0000
R11	0x000B0000
R10	0x000A0000
R9	0x00090000
R8	0x00080000
R7	0x00070000
R6	0x00060000
R5	0x00050008
R4	0x000400D5
R3	0x00030000
R2	0x00020053
R1	0x00016882
R0	0x00002000

  • 0 in reply to Lane Boyd
    Prodigy 10 points
    Dear Lane

    To achieve the design

    Customer design : input Xtal 25MHz,

    CDCI6214 Y1 clock output :54MHz

    Y2 clockoutput:25MHz

    Y clock output:50MHz

    Could you please kindly tell me which register and what value should I write in to achieve the request for each channel?

    Also, if I want to change the frequency which register and what value should I write in?
  • 0 in reply to peter hsieh
    TI__Genius 16845 points
    You can use the register settings from my last post. Write all registers in descending order from 0x44 to 0x00.
    You can use TICS Pro to generate the register settings for CDCI6214: www.ti.com/.../TICSPRO-SW . The GUI has a wizard to simplify frequency planning

    Kind regards,
    Lane
  • 0 in reply to Lane Boyd
    Prodigy 30 points

    Hi Lane,

    R65 0x00410F34
    R64 0x0040000D
    R63 0x003F0210

    Accroding to above data 

    R65 : write data 0x0F34 to register 0x0041

    R64 : write data 0x000D to register 0x0040

    R63 : write data 0x0210 to register 0x003F

    Is that correct?

  • 0 in reply to Jarvis Tsai
    TI__Genius 16845 points
    Yes, your understanding is correct

    Kind regards,
    Lane
  • 0 in reply to Lane Boyd
    Prodigy 30 points

    Hi Lane,

    If we want to control the output clock of each channel, how should i do?

    Example :
    If we want to control only Y1 clock output, which register should i write to? (also want to know Y2 and Y3)
    And if we want to control the value of output clock, which register should we write to and what's the setting rule of output value?

    please kindly tell us.

    Thanks.

  • 0 in reply to Jarvis Tsai
    TI__Genius 16845 points

    Registers 0x23 to 0x3F control the output channels. See datasheet Table 17 fore more information.
    I can send you a document over email. It is useful for calculating the required divider/mux settings to generate the output frequency. Please send me a request at clock_support@list.ti.com

    Kind regards,
    Lane