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LMK04610: Output clock phase is shifting by temperature change

Harson
Expert 3700 points
Part Number: LMK04610
Other Parts Discussed in Thread: LMK04616EVM, LMK04616, LMK04828, LMK04832

Hi, Team

My customer is using LMK04610, and they would like to keep the output clock has fixed phase delay than input clock.

This can be set by the zero delay mode by use feedback as Ouput Clock 7/8 descripted in datasheet.

But we found that once temperature is changing, for example from -40 to 25 ℃, the output clock phase will shift a lot.

I tried to reduplicated this in a LMK04616EVM which is the same problem.

Can you please help to check if this is expected or any way to optimize it to very little phase shift?

I've captured a video. CH1 is input CLKIN1, CH2 is OUTPUT9 which is same frequency as input of 122.88MHz.

Firstly I loaded the default setting from TICS, then I change it to the zero delay mode by setting feedback as OUTPUT 7(983.04MHz). It will locked well.

Then I will use freeze spray to cool down the LMK04616 on the EVM. The CH2 will shifting as video showed.

  • 0
    TI__Mastermind 28550 points
    Hello Harson,

    This recently came to my attention. I looked into it and confirmed similar behavior to what you see when driving from CLKin#.

    In the 0-delay feedback section 9.3.8 called Low Skew Mode in the LMK04610 datasheet, the phase comparison from output to is to PLL2 N and PLL2 phase detector. You will find improved 0-delay performance in PLL2 only mode. However when using PLL1, this issue will arise. To improve this or have 0-delay to PLL1, this is an issue that would need to be brought up with marketing.

    My recommendation is that 0-delay (or low skew mode) is effective only for PLL2 mode. If you require 0-delay for dual loop, PLL1 + PLL2. Please consider the LMK04832 or LMK04828/26/21 products. My understanding is that the phase would stay within +/- 1 period of the PLL1 phase detector frequency, but that period is often much larger than the period of PLL2, hence the appearance of the extreme shifting of phase.

    Note, the LMK04832 device and LMK0482x family are pin compatible to each other (not LMK0461x) and somewhat programming compatible except for the output section of the register map.

    Note, I also found on LMK04616, that CLKout6, not CLKout7 is used for the feedback point and CLKout9, not CLKout8 is used for the feedback point in the low skew mode. These clocks are inside the same pair, i.e. CLKout6 & 7 share a divider as do CLKout8 & 9, so normally wouldn't be an issue except for enabling delays. I need to confirm the LMK04610 feedback clocks to see if a similar documentation error exists and then update the datasheets.

    73,
    Timothy