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CDCE62002: Input clock tolerance

Satoshi Yoshida
Prodigy 660 points
Part Number: CDCE62002


Hi team,
Please let me know the tolerance of irregular input clock to CDCE62002.
(Please refer the attached xls.)
It seems CDCE62002 has locked with internal loop filter, but jitter is so high.

Best Regards,
Satoshi

CDCE62002.xlsx

  • 0
    TI__Genius 16845 points
    Hi Satoshi,

    Are you observing a static high on the PLL_LOCK pin? The input frequency varies, therefore it is possible that the VCO is not locking or not calibrating exactly to the average frequency (~27.2MHz).

    PLL lock detect is described in datasheet section 9.3.6 .The PLL lock detect window can be programmed from 2.1ns to 19.9ns. A wider lock detect window may be useful for this situation where the input clock period can vary from 33.7ns to 40.5ns.

    If the PLL is unlocked, first try to recalibrate the VCO, increase the lock detect window, or use a better reference clock.

    Kind regards,
    Lane