• State TI Thinks Resolved
  • Locked Locked
  • Replies 15 replies
  • Answers 6 answers
  • Subscribers 23 subscribers
  • Views 1961 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMX2581: PLL doesn't lock if ref clock is lost then re-input the reference clock

Toshihiro Watanabe
Genius 10235 points

Part Number: LMX2581

Hello,

In below process, LMX2581 doesn't lock PLL. Would you advise us how to lock PLL? We thought LMX2581 PLL is locked automatically when reference clock is recovered.

LMX2581 powerup -> PLL locked -> reference clock gone -> reference clock recovered.

Best regards,

Toshihiro Watanabe

  • 0
    TI__Guru** 122030 points
    Hi Watanabe-san,

    I don't have the problem with the EVM, could you share their configuration so that I can try again?
  • 0 in reply to Noel Fung
    TI__Genius 10235 points

    Hello Noel-san,

    Thank you for your support. The attached is the configuration. Please let me know if it is not enough.

    Best regards,

    Toshihiro Watanabe

  • 0 in reply to Toshihiro Watanabe
    TI__Genius 9920 points
    The attachment is not showed.
  • 0 in reply to Shawn Han
    TI__Genius 10235 points

    Hello,

    My apologize. I missed attahced. Please refer this.

    LMX2581configuration.xlsx

    Best regards,

    Toshihiro Watanabe

  • 0 in reply to Toshihiro Watanabe
    TI__Guru** 122030 points
    Hi Watanabe-san,

    The PFD_DLY is too big, the PLL becomes not stable. If you make it smaller, say 370ps, it will lock again when the reference clock is resumed.
    Couples of comment on the configuration:
    - Frac_order. My first choice is 3rd order. 2nd order may be better in some cases.
    - DLD_TOL is too big. Datasheet recommends 1.7ns.
  • 0 in reply to Noel Fung
    TI__Genius 10235 points
    Hello Noel-san,
    For DLD_TOL, there is a description which is "Larger settings are generally recommended".
    Is the larger setting no issue? Or is there possibility not detect reference clock loss? So far, we can detect the reference clock loss alarm by 18ns setting.
    When smaller value used, is there possibility to happen reference clock loss alarm detected frequently.
    Best regards,
    Toshihiro Watanabe
  • 0 in reply to Toshihiro Watanabe
    TI__Guru** 122030 points
    Hi Watanabe-san,

    DLD_TOL will affect the Lock Detect accuracy. If DLD_TOL is not set correctly (according to the table as shown in section 8.6.1.2.3), LD may indicate unlock even thought the PLL is locked, or vice versa.
    in this case, fpd=120MHz. So the phase detector will compare phases every 8.3333ns, which is even smaller than the DLD_TOL you have set.
    DLD_TOL should be set smaller than the fpd period.
  • 0 in reply to Noel Fung
    TI__Genius 10235 points

    Hello Noel-san,

    There is a case not locked PLL. If power cycle applied several times, there is a case to lock.

    Would you advise us what cases is thinkable? Please let me know what information is needed to narrow down this issue.

    Best regards,

    Toshihiro Watanabe

  • 0 in reply to Toshihiro Watanabe
    TI__Genius 10235 points
    Hello Noel-san,
    I forgot to write one thing. We follows the sequence which is written 8.5.2.of page 27 in datasheet.
    Best regards,
    Toshihiro Watanabe
  • 0 in reply to Toshihiro Watanabe
    TI__Guru** 122030 points
    Hi Watanabe-san,

    Would you try use the following settings and try again?
    Frac_Order = 3rd order
    Frac_Dither = disabled
    DLD_TOL = 1.7ns
    PFD_DLY = 370ps
  • 0 in reply to Noel Fung
    TI__Genius 10235 points
    Hello Noel-san,
    We tried this but still unlock issue is remaining. Would you advise us what is the thinkable reason? We can share the information if you need something.
    Best regards,
    Toshihiro Watanabe
  • 0 in reply to Noel Fung
    TI__Genius 10235 points

    Hello Noel-san,

    There is another question. PLL doesn't lock when reference clock is changed. Smaller shift like less than 40MHz, PLL still locked but when the frequency shift exceeds it, PLL seems out of lock.

    Procedure is below. I use 120.1MHz ref clock and 3320MHz output frequency.

    1) Apply 120.1MHz from SG

    2) configure LMX2581 for 3320MHz output

    3) the reference clock changed from 120.1MHz to 120MHz.

        -> then PLL is out of lock.

    The configuration is like below.

    Best regards,

    Toshihiro Watanabe

  • 0 in reply to Toshihiro Watanabe
    TI__Guru** 122030 points
    Hi Watanabe-san,

    For the previous question, if you were using the EVM, make sure you have disconnected and removed the power supply of the on-board 100MHz XO. Make sure the 120MHz input signal level is enough. If you were testing your board, what is the loop filter bandwidth?

    For the second question, can you measure the Vtune voltage when it is locked to 120MHz and when it is unlock with 120.1MHz reference clock?
    I think it is possible that the VCO cannot lock when the reference clock is change by 100kHz.
    There are 4 VCO cores in the chip. VCO4 range is around 3075MHz to 3800MHz. Within each VCO core, it is divided into 256 bands. So for VCO4, each band is approx. 2.832MHz.
    When it was first locked to 120MHz, the VCO calibration process had selected a certain band. When the frequency of the reference clock changes, the VCO will follow the change, so does the Vtune voltage.
    If the reference clock has change by 100kHz, ideally, the VCO should follow and change by 27.6666 (N-counter) x 100kHz = 2.76666MHz.
    - This change maybe marginal to this particular VCO band. Maybe the VCO will resume locked if the adjacent bands are selected.
    - Even though this VCO band can accept this amount of tolerance, the actually achievable VCO frequency maybe limited by the Vtune voltage. When the VCO is calibrated and locked, the Vtune voltage is usually set at 1.25V. The rails of Vtune voltage are 0V to 2.5V. If the required Vtune change is bigger than 1.25V, then the VCO may lose lock.
  • 0 in reply to Noel Fung
    TI__Genius 10235 points
    Hello Noel-san,
    The first question, it occurs our prototype. The loop filter BW is 57.44kHz.
    The second question, it occurs on the EVM. We will measure Vtune voltage then update later.
    Best regards,
    Toshihiro Watanabe
  • 0 in reply to Toshihiro Watanabe
    TI__Guru** 122030 points
    Hi Watanabe-san,

    The loop filter in the prototype is same as EVM.
    For the first question, since you have an EVM, can you verify it with the EVM? My EVM can regain lock when the reference clock is back.