Part Number: LMK03328
Hello
I would like to confirm about POR spec.
Could you explain me about spec of "VDROOP Allowable Voltage Droop" In the datasheet?
Best regards,
Tetsuro
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Part Number: LMK03328
Hello
I would like to confirm about POR spec.
Could you explain me about spec of "VDROOP Allowable Voltage Droop" In the datasheet?
Best regards,
Tetsuro
Vdroop is the max allowed voltage droop when the Core VDD supply pins are being ramped through the Vthresh region (2.72 V to 2.95 V) to avoid a potential brownout scenario, which could cause a failed POR cycle. The POR block relies on all Core VDD_x supply pins being powered. All Core VDD supply pins should ramp together monotonically. If the supply ramp is non-monotonic and exceeds the Vdroop spec, it is recommended to delay the low-to-high transition of the PDN input pin to ensure proper POR occurs as described on datasheet section 12.4.6.
Regards,
Alan
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Hello Alan,
I got supply waveform for power toggling. It seems the rump up time does not meet dVDD/dt recommendation. Doea it cause the problem?
Best regards,
Tetsuro