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LMK03328: POR spec

Part Number: LMK03328

Hello

I would like to confirm about POR spec.

Could you explain me about spec of "VDROOP Allowable Voltage Droop" In the datasheet?

Best regards,

Tetsuro

  • I has forwarded your question to related engineer. He will reply to you later.
  • Han,

    Thank you very much for your support.
    I have one more question. Is the supply pin for POR block VDD_DIG?

    My customer is now facing I2C communication stop problem and it seems brownout of the POR supply causes the issue because the communication resumes by PDN toggling.


    Best regards,
    Tetsuro
  • Vdroop is the max allowed voltage droop when the Core VDD supply pins are being ramped through the Vthresh region (2.72 V to 2.95 V) to avoid a potential brownout scenario, which could cause a failed POR cycle.  The POR block relies on all Core VDD_x supply pins being powered.  All Core VDD supply pins should ramp together monotonically.  If the supply ramp is non-monotonic and exceeds the Vdroop spec, it is recommended to delay the low-to-high transition of the PDN input pin to ensure proper POR occurs as described on datasheet section 12.4.6.

    Regards,
    Alan

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  • Hello Alan,

    I got supply waveform for power toggling. It seems the rump up time does not meet dVDD/dt recommendation. Doea it cause the problem?

    Best regards,

    Tetsuro

    LMK03328_Supply.pdf

  • In the PDF file you shared, it appears the 3.3V supply ramp is around 2 ms, which is within spec.  I don't see an issue with it.

    Alan

  • Hello Alan,

    Thank you for confirmation.
    I missed to read the scaling.

    By the way, I got additonal report from the customer. They confirmed the I2C comunication stop problem without Power on/off (no brownout)

    The customer repeated following sequence, and the I2C stopped after 1000 to 1200 times of access.

    PDN:low -> 1s -> PDN:high -> 1s -> I2C read (dummy) -> I2C read & compere (Address : 0x0C data : 0xd9)

    Could you advice me why this happen?

    Tetsuro
  • Hello,

    Can you please send the customer's LMK03328 schematic to clock_support@list.ti.com, so the Clocking Applications team can review their use case? In the email, please also share the customer name, project name/stage/schedule, and any other relevant details (no. of parts/board tested, failure rate, etc.) to help us prioritize the request accordingly. Please also provide the chip top mark info, so we can check if it is the current production silicon or earlier engineering silicon.

    Thanks,
    Alan