Hi Team,

My customer is interested to use the CDCE925 with the SN65LV1224B. The SN65LV1224B has a +/-100ppm requirement on the clock input. With this, they want to understand if the CDCE925 will work:

The clock generator is another TI part, the CDCE925PWG4, driving 3.3V lines.  Its driving crystal is 27MHz with a 50ppm spec, so that uses half our tolerance budget.  The cycle-to-cycle jitter is the number we need for figuring out how much noise this clock generator chip contributes, and it’s stated in time (60-100ps for output Y3) so I will need to dig into the code to find out how we configure that frequency before I know what the fractional noise is.  Do I also need to add peak-to-peak period jitter?  (We are using all five outputs—do the “1 PLL” vs “2 PLL” lines relate to this?)

Appreciate your insight.

Regards,

~John