Kpfd and vco cap

Pankaj,

1. Kpd: If the part is programmed to 15 mA, this means that if the charge pump is on fully with 100% duty cycle, it will source or sink 15 mA. Some charge pumps are in the 100's of uA range, especially those for low bandwidht PLLs like in jitter cleaners, but this is in the mA range.
But realize that the duty cycle of the charge pump is typically very low in the locked state, so the majority of the time this charge pump is off.

The current sourced when the charge pump is on is 15 mA, not 15 mA/(2pi). Now if you want to convert this to current/radian, you divide by 2pi. But I discourage doing this because the VCO gain is multiplied by 2pi to convert from Hz to radian, so the 2pi just cancels out.

2. 15 GHz: PLLatinum sim can be used DC to daylight and certainly above 15 GHz. Now if you choose a part that does not go above 15 GHz, it might warn you and turn boxes red, but you do not have to heed these warnings. Also, you can do the custom PLL. The math or the tool does not break down above 15 GHz just because that's our highest frequency VCO.

3. VCO Cap: This is an inherent property of the VCO. Telling the tool that it is 0 because it is inconvenient does not change the actual silicon. PLLatinum sim will model whatever you say, so it is the job of the user to give it the right information. Maybe it would be simpler if this VCO capacitance was locked from the user being able to choose, but sometimes these simplifications can frustrate users. For instance, if you have your own external VCO, you can find this parameter in the VCO datasheet. Or perhaps you want to see the impact on your design if the VCO capacitance was to vary from default value. Or perhaps you are seeing some strange effect and want to see if the VCO capacitance could be a plausible explanation. We have no guarantee or high confidence measurements for VCO capacitance. This is an estimate from design.

4. Jitter: The jitter is calcualted from the phase noise. In the graph, you can see it includes PLL, VCO, and loop filter. You can go to the phase noise tab and add your input reference noise if you like; if you don't PLLatinum sim assumes noiseles input reference. The "PLL" portion includes noise from the N divider, R divider, input path, and charge pump. These are all lumped together in to the parameters of PLL flicker noise and PLL figure of merit.

Regards,
Dean

Pankaj,

So if you tell PLLatinum sim that C1 = 18 pF and VCO input capacitance is 0, then what you will likely find is that when you actually build it, you get a much narrower loop bandwidth than you designed before because the VCO input capaciance is not zero, but much higher. Also, there is a minimum high order capacitance, that the tool is probably warning you about. If the capacitor next to the VCO is < 3.3 nF, then the VCO phase noise degrades. The tool defaults to 1.5 nF limit which leads to about 1 nF degradation. In other words, don't ignore these.

To get around this, you need to maximize the phase detector frequency and also the charge pump gain. You can use the advanced mode to design minimize jitter. Also, click on the "design tips" on the loop filter.

For your change pump current, you would put 6.5 mA in your case, but you should really increase to 15 mA to help with the issue of the small. As for the duty cycle, it is 100% only in the extreme cases of being unlocked, in the locked condition, it is <1% in the steady state.

When the PLL is locked, the charge pump sources current very briefly and then it goes high impedance. Then it sinks current very briefly and goes high impedance, then it repeats.

Regards,
Dean

7411.LMX2594 Minimum High Order Cap for Vtune.pdfPankaj,

PLLatinum sim does not model all effects and does not model the effect of violating the recommendation of going below the 3.3 nF.  On the loop filter design tab, click on the filter design tips button and it talks all about this.  Also see attached report.

As for the "small", I am talking about the small loop filter capacitor next to the VCO  18 pF is really small.  Not only will it be swamped out by the VCO input capacitance, but it will lead to high VCO pahse noise that is not modeled by PLLatinum Sim.  But if you double your charge pump gain, this capacitance doubles and it helps a little, although 36 pF for C1 is still way too small.

Regards,

Dean

Pankaj,

This offset is offset from the carrier. So for instance, if C3_LF is 120 pF, the impedance is 997 ohm and the phase noise degradation at 100 kHz offset is 4.4 dB.

As for current from the charge pump, it depends on duty cycle. Duty cycle is pretty low, like 1%, so more like 15e-03*1volt*1%

Regards,
Dean

Hi Pankaj,

See feedback on the other post.