LMK04610: Periodic Unlocking of PLL1 on startup.

I looked at the status output set as HOLDOVER_EN and it appears that holdover is not active during the majority of the PLL1 lock time. I have attached a screenshot of the PLL1 lockdetect and Holdover status waveforms. I also tested a register set with Holdover disabled and the periodic unlock behavior is the same.

Yellow is the holdover status and blue is the PLL1 lock detect signal. It appears after about 150ms the holdover is de-asserted and does not re-assert. The solid blue region is where the PLL1 lock detect is doing the periodic toggle as described in my original post.

Shawn,

1.) I monitored the VCXO output frequency using a spectrum analyzer and saw a gradual increase to ~125MHz from power on until the lock detect indicated a stable lock. The power up frequency was typically a couple Khz below the 125MHz VCXO freq. I saw corresponding behavior when monitoring the VCXO control voltage, which gradually increased to a stable value of 2.1v.

2.) I tested a pll1 configuration with a 1.25MHz PFD and It did decrease the lock time to 0.75sec ( lock indicated by the DLD). The DLD output was still indicating the periodic unlock events as described previously just with a faster decay to stable lock indication. I have attached a screenshot of the DLD signal to clarify.

3.) The system is usually running for half an hour or more before my testing so the OCXO should be stable.

Do you expect there to be some locking and unlocking indicated by the DLD during startup? Also, it seems to me the behavior is likely tied to the DLD itself not the actual PLL loop given the stable increase of the VCXO freq/control voltage, but a more experienced opinion on this would be appreciated.

From my understanding increasing the PFD frequency will also increase phase noise passed from the OCXO, is this just a trade off that needs to be made between phase noise and lock time?

Thanks for the help,

Seth Kreitinger

Hi Seth,

Something wrong in E2E make no response in E2E. Let me clarify the Digital lock detect signal.

It is expected in PLL locking.

As datasheet showed, phase error should be less than a specified window size (ε) for continuous enough times (PLLx Lock Count), one time violation would reset count. If the violation happened after locked, digital lock status will change from lock to unlock.

In PLL locking, feedback clock phase is tuned to close to reference clock phase, it can have some frequency ringing around target frequency. In PLL locking, because frequency had not been locked, phase relationship on PFD (phase frequency detector) is moving.Ahead, close, behind will periodically happen until PLL locked. When we set a small PLLx lock count, we can saw obvious periodic lock and unlock on digital lock detect status.

For why large PLLx Lock Count can make a fast lock, I had not thought of the whole flow, but Figure 40 can give some clues.

Datasheet also shows "Digital Lock Detect Frequency Accuracy", which also related with above figure.

Hope we can find the cause soon. let us know your thought. I had looped my colleagues in E2E system for more discussion.

Thanks.

Best Regards,

Shawn