I bought a CDC5801A for the purpose of generating the phase-locked RF signal with arbitrarily delay.
Here is my use;
1. I input the RF signal (82.5 MHz) to the "REFCLK".
2. I get the multiplied or divided RF signal from the "CLKOUT/CLKOUTB".
Then, I want to control the delay of CLKOUT vs REFCLK, but I couldn't understand the function of DLYCTRL.
According to the manual, when CLKOUT = 50 MHz in the "Divide by 2" situation, step delay size is 6.5 ps.
In this case, if I input the 10 rising edges to the DLYCTRL, is the delay with 65 ps generated?
If this is correct, should I prepare some RF source and counter for controlling the delay size?
Sincerely,
