LMK04832: Single or dual PLL mode?

art arty

Part Number: LMK04832

I have very "good" input reference to LMK, but it is relatively slow (10 MHz). SYSREF output should have deterministic phase relationship to the input reference. Is is better to use LMK in single PLL or nested 0-delay dual PLL mode? I know that two PLLs can help if the input reference is bad, but I also think that they may add an additional noise in my case.

over 6 years ago

0 Dean Banerjee over 6 years ago

TI__Mastermind 28001 points

Art,

I would use dual loop mode. Although your input reference is clean, this is very low frequency and you could run the phase detector much higher frequency for PLL2, which will result in better jitter.

But the only catch is that then you need a higher frequency VCXO. If you have one, then this sets the jitter, and PLL1 has no impact. But the key is that you need a good high frequency (100 MHz) VCXO. If you don't want to supply this, then use single-loop mode and give up a little jitter.

Regards,
Dean

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LMK04832: Single or dual PLL mode?