• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 21 subscribers
  • Views 439 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TLC555: Output dependency on supply voltage/temperature

TLC555: Internal error of timing interval

Shota Mago
Expert 8440 points
Part Number: TLC555


Hi team,

My customer provided some questions in terms of timing interval as follows.

Datasheet shows "Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run.".

  1. How many samples are assumed in this sentence?(only 1 CLK or many other?)

  2. If above sentence assumes 1CLK, what about 1000CLK?
    The customer understands as below.
    For example, when designing with a CLK period of 1 sec,
    CLK cycle: 0.99 sec → 1.01 sec → 0.99 sec → ... and so on, the average value is 1 sec, so the error as a whole system(CLK) is 0%, but the error per 1 CLK is 1%.
    CLK cycle: 1.01 sec → 1.01 sec → 1.01 sec → ... and so on, the average value is 1.01 sec, so the error as a whole system(CLK) is 1%, but the error per CLK is 0%.
    Which understanding is correct?(or wrong?)

I'm looking forward to hearing back from you.

Best regards,

Shota Mago

  • 0
    TI__Guru**** 167976 points
    Shota-san,

    My interpretation of the text is that error applies to every output pulse period of any device in question. The pulse output period in a-stable mode will be within +/-3% of the average pulse output period of basically the whole population of TLC555 produced. Although the exact text says 1 device per process run. This covers the timer parameters only; capacitor and resistor, and VCC changes must be considered separately.

    Looking at the resistor and capacitor range gives the lowest frequency covered at 48 Hz = 1.44 / 0.1uF / (2*100k+100k)
    Running slower is fine and I suggest increasing capacitance to get there. At all low frequencies, the propagation delay is all but meaningless. At lowest frequencies, it is best to keep noise away from control pin cap and timing cap signals. Vdd must remain constant over the period for best accuracy. At high temperatures consider the leakage current of timer and timing capacitor.
  • 0 in reply to Ron Michallick
    TI__Expert 8440 points

    Hi Ron-san

    Thanks for kind explanation.
    Let me simplify customer's question.

    When TLC555 runs at 20.8ms cycle(48Hz) with ideal resitor/capacitor, initial accuracy should be within ±3%.
    After initial phase(stable condition), there is no possibility to cause more error such as 5% by internal circuit variation when we assume ideal resistor/capacitor.
    Is this understanding correct?

    Best regards,
    Shota Mago

  • 0 in reply to Shota Mago
    TI__Guru**** 167976 points
    Shota-san,

    Your understanding is valid.
  • 0 in reply to Ron Michallick
    TI__Expert 8440 points
    Thanks Ron-san!

    Best regards,
    Shota Mago