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LMX2592: settings for best phase noise and spurs with a 1Hz step size from 4.3GHz to 8.3GHz?

JohnP
Intellectual 470 points
Part Number: LMX2592
Other Parts Discussed in Thread: LMX2492, LMX2581

Dear Experts

I am using the LMX2592 to generate a Local Oscillator (LO) for a  receiver application where phase noise and spus are important.  The frequency range of the LO is approximately 4.3 to 8.3GHz with a step size of approximately one Hertz.  The reference is a very low noise 2GHz source which feeds a programmable divider to bring the frequency within range of the LMX2592 OSCin.  Please can you recommend input path frequencies and settings (modulator order, PFD delay, charge pump current etc.) vs output frequency to minimize phase noise and spurs?

As the output frequency range includes multiples of the reference (6 and 8GHz) integer boundary spurs are possible.  Please can you suggest how to use the multiplier to avoid these integer boundary spurs?  To help me understand the issues, please can you give me a good example of integer boundary spur avoidance using the multiplier on the evaluation board?

Thanks in anticipation.

John

  • 0
    TI__Guru** 107030 points
    Hi John,

    What is your target phase noise?
    you can refer to the following appsnote on the theory of multiplier.
    www.ti.com/.../snaa289
    Datasheet section 8.1.5.1 also has an example.
  • 0 in reply to Noel Fung
    Intellectual 470 points
    Hi Noel

    Thanks for the information. My target phase noise jitter is 150fs rms integrated from 40Hz to 40MHz.
  • 0 in reply to JohnP
    TI__Guru** 107030 points
    Hi John,

    150fs is not difficult to meet in general, however, since the step size is in Hz, you will encounter a lot of fractional channels and in some channels, the spurs could be big enough to greatly increase the jitter to over 1000fs.
    Do you need to meet the jitter spec for all channels?
  • 0 in reply to Noel Fung
    Intellectual 470 points

    Hi Noel

    Yes I'm finding that I can meet 150fs over thousands of channels on average, but not all channels. On some channels there are huge phase noise issues which can mostly be fixed by changing the PFD delay setting which does not necessarily agree with table 2 in the datasheet.

    For example with Fpd at 2e9/14 (142,857,142.9Hz) N div at 18, 3rd order MASH, output frequency 5,184 999 999.9Hz and the PFD delay set as per the datasheet at 2 (6 cycle delay): with one instance of the device I measure approximately 143fs jitter. However with three other instances of the device I measure 13ps jitter! The jitter can be improved to 143fs by setting the PFD delay to 1 (4 cycle delay). Can you explain the difference?

    Is it to be expected to have to alter the PFD delay from device to device to get good performance? I don't want to have to tune each device independently for every frequency step. Can you suggest a better way to get good performance at all frequency steps on all devices?

    John

  • 0 in reply to JohnP
    TI__Mastermind 28001 points
    John,

    Fractional spurs are definitely a concern with 1 Hz channel spacing. You might find that the programmable input multiplier is useful to shift the phase detector frequency and can reduce many (but not the integer boundary spur itself) of the fractional spurs. The multiplier may add some phase noise, but your fractional spurs are likely going to dominate the jitter anyways.

    As for playing with PFD_DLY_SEL, I think that you do not want to choose a value smaller than one in the datasheet, but maybe a larger one might be more acceptable. You definitely want to be somewhat cautious with this to avoid it being a part-specific optimization for each and every part. So in your example, reducing PFD_DLY_SEL might be something I would be careful about. Also, it might not hold even for the same part over temperature. This being said, 13 ps vs 143 fs seems like a pretty drastic difference

    Also, ensure that PLL_N_PRE is the smaller divide by 2 value for better fractional spurs.

    Regards,
    Dean
  • 0 in reply to Dean Banerjee
    Intellectual 470 points

    Hi Dean

    Thanks for helping. I'm not exactly sure what you mean by 'Also, ensure that PLL_N_PRE is the smaller divide by 2 value for better fractional spurs.'. Please can you explain a little further?

    Thanks

    John

  • 0 in reply to Dean Banerjee
    Intellectual 470 points
    Hi Dean

    Another question: why does the datasheet reference PFD delay to N divider? Your most excellent book 'PLL Performance,....' seems to reference it to Fpd?

    Thanks

    John
  • 0 in reply to JohnP
    TI__Mastermind 28001 points
    John,

    For my book, I talk about the single PFD archtecture and the PFD_DLY applies to devices like the LMX2492 and LMX2581.
    The LMX2592 has a dual PFD architecture that is a little different. This does put a delay in the N divider had sort of has a similar effect, but not exactly. For instance, if you set this too low beyond datasheet legal values, you can cause the PLL to lose lock under some circumstances.

    Regards,
    Dean
  • 0 in reply to Dean Banerjee
    Intellectual 470 points

    Hi Dean

    Ok thanks, so for the LMX2592 it makes sense to optimise the PFD delay per N divider setting.

    Please could you also explain your 'Also, ensure that PLL_N_PRE is the smaller divide by 2 value for better fractional spurs.'?

    Thanks

    John

  • 0 in reply to JohnP
    TI__Mastermind 28001 points
    John,

    When operating in fractional mode with a Pre-N divider of 2, this reduces the resolution by a factor of 2 and doubles the frequency deviation. What this means is that he spurs (before filtering) are 6 dB higher and 1/2 the offset frequency (because you have to make the resolution 1/2 to compensate for the divide). Now when you change this to 4, the offset is now 1/4 and the spur is 12 dB higher theoretically. So therefore, the PreN divide of 2 is better for fractional spurs than PreN of 4.

    Regards,
    Dean
  • 0 in reply to Dean Banerjee
    Intellectual 470 points

    Hi Dean

    Thanks that answered that query.

    My main problem though is still unresolved - what are the best settings for phase noise and spurs across my frequency range?

    Best regards

    John

  • 0 in reply to JohnP
    TI__Mastermind 28001 points
    John,

    OK, to restate the problem, you want to tune 4.3 to 8.3 GHz in 1 Hz steps. Your input frequency is 2 GHz source followed by a divider.
    There's always some trial and optimization, but here's a starting point.

    Fix:
    MASH_ORDER=3

    Now have 2 settings:
    Setting 1:
    Fosc = 2000 MHz/10 = 200 MHz
    Fpd = 2000 MHz/10 = 200 MHz
    CPG = 15 mA
    PLL_DEN = 2000000
    FNUM steps by 1

    Setting 2:
    Fosc = 2000 MHz/8 = 250 MHz
    Fpd = 2000 MHz/8 = 250 MHz
    CPG = 12 mA
    PLL_DEN = 2500000
    FNUM steps by 1

    Now define Fvco%Fpd as the distance to the closest integer boundary. So if your VCO is 6505 MHz and Fpd = 200 MHz, then Fvco%Fpd would be 95 MHz

    Now for each frequency calculate:
    x = Fvco % 200 MHz
    y = Fvco % 250 MHz

    If x>y, choose setting 1, else choose setting 2.

    So this should take care of all frequencies that are far away from multiplies of 2 GHz.

    But what about near (say within 3 MHz) of 6 and 8 GHz, what phase detector frequency then?
    For this, I would try the programmable input multiplier. For instance, you can try this:

    Fosc = 2000MHz/8 = 250 MHz
    PLL_R_PRE=6
    MULT=5
    Fpd = Fosc/PLL_R
    FDEN=1250000000
    FNUM steps by 6

    Regards,
    Dean
  • 0 in reply to Dean Banerjee
    Intellectual 470 points

    Thanks very much for the suggestions.