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LMK04826: Is there a spec for the internal phase difference between parts?

Layne Jakahi
Intellectual 820 points
Part Number: LMK04826


Hello

I have a particular board that is showing the phase difference after the R divider and N divider is bigger than other cards for PLL1.  We are using the STATUS pins and an oscope to see what the signals look like after the dividers.  This means that we have to increase the window size in order to see the lock LED light up.  This doesnt make much sence as it should be the same for all cards.

I have replaced every component in the loop filter and nothing changed.  Since the loop is internal to the LMK0426, is this a normal thing where sometimes there is a phase difference between parts? Our other cards will show that the signals are aligned within 4nsec, but on this card its like 9ns. 

Please assist.  I didnt find anything in the datasheet that mentions part variations between lots.  I am thinking of replacing the LMK0426 just to see if it changes.

Thanks

Layne

  

  • 0
    TI__Mastermind 28560 points
    Hello Layne,

    The issue is with the leakage of your VCXO. I expect if you swap the VCXO of the board in question with another board, the phase difference will follow the VCXO.

    You can mitigate the impact of leakage of VCXO by designing PLL1 with high charge pump currents on PLL1. This will increase your capacitors but the ratio of leakage current to charge pump current will decrease. Increasing PLL1 phase detector frequency will also help to mitigate this issue. Finally, using an op-amp to buffer the VCXO input would alleviate this issue.

    73,
    Timothy
  • 0 in reply to Timothy T
    Intellectual 820 points

    hi timothy

    oh yes, yesterday i also changed out the ocxo with a brand new one and no change.  but as you have suggested, i may have to try to use one from one of the working boards just to see if anything changes.  but if it doesnt, i have no idea what to do next except to change out the LMK.

    right now we are using 1550uA for the charge pump current so we cant go any higher.  we are also using the highest PFD frequency too.  

    thanks 

    Layne

  • 0 in reply to Layne Jakahi
    TI__Mastermind 28560 points
    Can you advise what your phase detector frequency is for PLL1?

    73,
    Timothy
  • 0 in reply to Timothy T
    Intellectual 820 points

    LMK04826B PLL1 LOCKING PROBLEM.pdfHi, Timothy,

    Our PD frequency is 1.536MHz.

    We just found out a very odd problem.

    Let's say I have a master card that generates ref clock and a slave card that receives the ref clock. the ref clock from the master card is fed into CLKIN0 differential pins of LMK PLL1 of slave card.

    we are monitoring the slave card PLL1 R and N divider output on the oscillator scope when PLL1 locks. By keeping the same slave card, but swapping different master cards, we get different relationship between the R divider and N divider output on slave card PLL1, which will be attached during this post.

    This is very abnormal since the whole purpose of Phase lock loop is to make R divider and N divider phase relationship constant.

    I am aware of that if there is a leaky loop filter capacitor or leaky VCO on PLL1, the phase may not be aligned exactly between R and N divider output, but the phase offset should be constant if I keep the slave card the same。

    By the way, We are feeding in a ref clock of 98.304Mhz, it is pulse width modulated ref clock. The pattern is three highs one low and then one high three lows, but the rising edge rate is constant at 98.304Mhz. both the R and N divider is 64, which comes to the PD frequency of 1.536MHz.  

    Attached you will find pictures of our experiment in the pdf file.

    Thank you so much for your help, we have been stuck on this for a couple of days and run out of ideas to try.

  • 0 in reply to Layne Jakahi
    TI__Mastermind 28560 points
    Hello,

    Responded in other thread
    e2e.ti.com/.../2904535

    73,
    Timothy