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Original question:

Custom PLL design

Custom Phase locked loop design

Pankaj Chugh
Prodigy 240 points


Hi,

I am trying to design a custom PLL clock for 12.5GHZ and 25GHZ but I am not getting the jitter specs of 150fs,  I am looking for.

I have tried to use "optimize jitter" option but, the simulation keeps running forever.  The tool does not spit out the R1, C1 and C2 values it just shows calculating in the PLLatinum window.

Is there an issue with the tool download or why the simulation is not doing "optimize jitter"

Can you suggest a way I can compare 12.5 GHZ and 25GHZ PLL clock for jitter specs of 150fs as to which is better for 25GBPS SERDES in terms of jitter, area, Power dissipation.

Basically, I can have 12.5 GHZ clock or 25GHZ clock for transmitter PLL in SERDES . Once I compare the jitter values for both frequencies, I can decide the clock speed(12.5GHZ or 25GHZ) I have to design the transmitter  PLL for SERDES

 thanks

  • 0
    TI__Mastermind 28021 points
    Pankaj,

    This can't be answered without knowing more about the PLL and VCO noise.

    Without knowing the PLL noise and VCO noise, the optimize jitter is meaningless as this is based on the PLL and VCO noise. In the tool, you can enter the VCO noise, but I see the PLL noise is locked out for editing, but you can still load something in. It does take longer than expected. What it does is first sweep the loop bandwidth and then does a quick search, but it only updates the screen when it finds something better. I will look and see if any optimizations are possible, and if we find something, we will update it the next time we release PLLatinum Sim (next part release of LMX device).

    As for comparing clocks, if they were the same jitter, the 12.5 GHz PLL should be exactly 6 dB better than the 25 GHz PLL.

    Regards,
    Dean
  • 0 in reply to Dean Banerjee
    Prodigy 240 points
    Hi Dean,

    As for comparing clocks, if they were the same jitter, the 12.5 GHz PLL should be exactly 6 dB better than the 25 GHz PLL.

    When you say 6db better 12.5GHZ clock over 25GHZ clock when jitter is same , what is better by 6 db.

    regards
    -pankaj
  • 0 in reply to Pankaj Chugh
    Prodigy 240 points

    Hi,

    Using PLLatinum SIm

    I am trying to get a jitter of 150fs with a PLL Loop Bandwidth of 2MHZ using PLLatinum sim (Custom PLL) I tried various combinations of R1, C1, C2. but if I get jitter, I don't get PLL Loop Bandwidth and vice-versa.. The current I change from 5mA - 15mA. Should I make the current higher. How much current should I burn for 150fs jitter . If I use large current, it still does not give the correct result. I added VCO noise, noise of Crystal (-145dBc/Hz)  The integration limit I have used is starting from 1 MHZ to FCLK/2. FCLK is 12.5GHZ..Application is 25GBPS SERDES.

    To get 150ps the R1 value is in ohms (47 ohms) and C1 and C2 are 250pF and 8200pF (do not remember the exact value) but is too high.

    How do I get jitter of 150ps and PLL Loop Bandwidth of 1MHZ-5MHZ.  Should I increase Icp(Kpfd) to 50mA or even higher or it's not recommended. If we use that kind of currents then ESR of the capacitor might matter just as in an LDO regulator.

    I have to do the same exercise for 25GHZ PLL clock and then decide which  PLL (12.5GHZ or 25GHZ) is better in terms of performance for 25GBPS SERDES.

    regards

    -pankaj

  • 0 in reply to Pankaj Chugh
    TI__Mastermind 28021 points
    Pankaj,

    "custom" PLL means that it is your PLL and you can define it however you want. However, since it's your PLL, the simulation is only as good as what you tell PLLatinum sim about your PLL.

    Now if you want this very wide bandwidth, then you do need: very low N divider value, very high charge pump current, very high VCO gain, or an op amp to isolate the VCO capacitance. So yes, 50 mA mithg be reasonable.

    But as it is your VCO, the first question to know is can your VCO on it's own do 150 ps. If so, maybe try a narrower lop bandwidth.

    As for the PLL noise, PLLatinum Sim assumes very high noise for a "custom" device for the PLL. So if you think that it's unrealisitc for your PLL, your only option is to disable the PLL noise and assume that the input reference dominates over the PLL.

    As for the jitter, a 12.5 GHz clock would have to have jitter that is 6 dB better than a 25 GHz to get the same jitter.

    Regards,
    Dean
  • 0 in reply to Dean Banerjee
    Prodigy 240 points

    As for the PLL noise, PLLatinum Sim assumes very high noise for a "custom" device for the PLL. So if you think that it's unrealistic for your PLL, your only option is to disable the PLL noise and assume that the input reference dominates over the PLL.

    ABOVE MESSAGE BY YOU

    ============================

    1) What is PLL noise. I have already enabled LPF noise, output divider noise, VCO noise ( I have done a manual override, and added VCO Phase noise data from phase noise plot in cadence) , Crystal oscillator noise. If i disable PLL noise  I am getting good jitter numbers. My VCO noise in cadence simulation for LC VCO is 1.77ps for Integration limit from 12.5KHZ to FLCK/2 and 41fs for integration limit from 1 MHZ to FLCK/2.  FCLk is 12.5GHZ.. Also, what is the realistic PLL noise I should put in PLLatinum sim for custom PLL or should I disable it and assume it to be as much as VCO noise of 41fs as obtained in simulation in cadence.

    2) Also, the integration limit  I am assuming is 1MHZ to FCLK/2. FCLk is 12.5GHZ. If I assume Integration lower limit to be 12.5KHZ then the jitter numbers worsen. I have been told to use higher lower Integration limit. I have been told that it depends on application. So, for our application, 25GBPS SERDES, I have to assume Lower Integration limit as 12.5khZ or 1 MHZ for calculating rms random phase jitter or even higher. Please do let me know your thoughts.

    Please let me know

  • 0 in reply to Pankaj Chugh
    Prodigy 240 points

    Also, I simulated stand alone VCO in Cadence  for 12.5 GHZ and 25GHZ. The RMS jitter for 25GHZ VCO is half of RMS jitter for 12.5HZ VCO. The KVCO of 25GHZ is double of 12.5GHZ.

    The reason is that when we do standalone VCO in cadence , the PLL loop does not correct. the jitter. 

    So based on the simulations in Cadence  I should go for 25GHZ VCO because of better jitter specifications.

    Is it that when I put PLL  in a closed loop then the PLL will exhibit less jitter for 12.5 GHZ than 25 GHZ even though VCO behaves opposite.. What are your thoughts.

    thanks

  • 0 in reply to Pankaj Chugh
    Prodigy 240 points
    One more question, I have used Icp as 50mA as you suggested I am getting the Loop Bandwidth that I want. When I do Charge Pump in circuit, I should have current source for UP and DN networks to be 50mA each. Am I right. So there will be a PMOS current source of 50 mA on top and NMOS current source of 50 mA at the bottom for a single ended charge pump. Please advise.
  • 0 in reply to Pankaj Chugh
    TI__Mastermind 28021 points
    Panjaj,
    Yes, this is typically how it is done.
    Regards,
    Dean
  • 0 in reply to Dean Banerjee
    Prodigy 240 points
    As for the PLL noise, PLLatinum Sim assumes very high noise for a "custom" device for the PLL. So if you think that it's unrealistic for your PLL, your only option is to disable the PLL noise and assume that the input reference dominates over the PLL.

    ABOVE MESSAGE BY YOU. YOU HAVEN'T ANSWERED THE QUESTIONS BELOW. WOULD APPRECIATE A REPLY FROM YOUR SIDE

    ========================================================================================================

    1) What is PLL noise. I have already enabled LPF noise, output divider noise, VCO noise ( I have done a manual override, and added VCO Phase noise data from phase noise plot in cadence) , Crystal oscillator noise. If i disable PLL noise I am getting good jitter numbers. My VCO noise in cadence simulation for LC VCO is 1.77ps for Integration limit from 12.5KHZ to FLCK/2 and 41fs for integration limit from 1 MHZ to FLCK/2. FCLk is 12.5GHZ.. Also, what is the realistic PLL noise I should put in PLLatinum sim for custom PLL or should I disable it and assume it to be as much as VCO noise of 41fs as obtained in simulation in cadence.

    2) Also, the integration limit I am assuming is 1MHZ to FCLK/2. FCLk is 12.5GHZ. If I assume Integration lower limit to be 12.5KHZ then the jitter numbers worsen. I have been told to use higher lower Integration limit. I have been told that it depends on application. So, for our application, 25GBPS SERDES, I have to assume Lower Integration limit as 12.5khZ or 1 MHZ for calculating rms random phase jitter or even higher. Please do let me know your thoughts.

    Please let me know

    3) Also, I simulated stand alone VCO in Cadence for 12.5 GHZ and 25GHZ. The RMS jitter for 25GHZ VCO is half of RMS jitter for 12.5HZ VCO. The KVCO of 25GHZ is double of 12.5GHZ.

    The reason is that when we do standalone VCO in cadence , the PLL loop does not correct. the jitter.

    So based on the simulations in Cadence I should go for 25GHZ VCO because of better jitter specifications.

    Is it that when I put PLL in a closed loop then the PLL will exhibit less jitter for 12.5 GHZ than 25 GHZ even though VCO behaves opposite.. What are your thoughts.
  • 0 in reply to Pankaj Chugh
    TI__Mastermind 28021 points
    Pankaj,

    1. The PLL noise is based on the PLL figure of merit, which is agregated noise of the PLL Input Path, R divider, N divider, and charge pump rolled up into simple parameters of the PLL figure of merit and PLL normalized 1/f noise. The charge pump is the heart of the PLL and typically dominates the figure of merit, but not aways. These are not numbers we get from the design of the PLL, but rather something we measure in the lab and store in the database. For the PLL noise, we measure with a wide loop badnwidth and subtract fit a noise profile constructed from PLL 1/f and PLL figure of merit to match our measurement. So in your case, the numbers in there are for older PLLs and I don't kow what to expect. If you have a noisier crystal input, then this could dominate over the PLL noise anyways. All this being said, as this sounds like this is your PLL you are designing (as opposed from using from TI), so ultimately you are the one who is going to have to figure out what noise of it is.

    2. On integration limit is application specific. I'm not a SERDES expert at all, but I thin taht 12.5 kHz sounds much lower than you need. In my old (very possibly incorrect) notes, I have integration limits of 637kHz to 12.5 Mhz for 1 GB ethernet, 1.875 MHz to 20 MHz for 10 GB ethernet. But please don't take these numbers to the bank as I'm no ethernet specialist. But in any case, it makes me think that 12.5 kHz does sound low. Sometimes people use 12kHz-20MHz for integration limit, but this is for SONET.

    3. When you lock the VCO to the PLL, the PLL can likely clean up the close-in phase noise. From Q1, it's not clear what to expect for teh PLL noise, but likely at lower offsets of <50 kHz, the PLL might dominate, but that depends on the PLL noise.


    As for your jitter simulations, if you say the 25 GHz VCO is half the jitter of the 12.5 GHz VCO, this suggests to me that you are saying the 25 GHz VCO has the same phase noise as the 12.5 GHz VCO. If this is the case, the jitter is half. But typically as you go higher in frequency, the VCO phase noise degrades. Typically twice the frequency is 6 dB higher jitter, but this is part specific and not always the case.

    I think that what you are saying is that for 12.5 GHz, you get better jitter when you lock it up to a PLL, which is what one would expect. However, this depends on your integration lmiit. If you use 12.5 kHz, then it makes sense. However, I do wonder if this is the right integration limit, or you should have something much higher. If it should be somethign much higher, then you will find that locking it to a PLL does not help.

    For 25 GHz, I would also expect the PLL to improve the jitter. However, it soulds like you are assuming the 25 GHz VCO has no worse phase noise than the 12.5 GHz VCO. IF this is the case, it makes sense. The PLL noise would be 6 dB higher at 25 GHz. However, just be sure that your 25 GHz VCO is really no higher phase noise than the 12.5 GHz VCO.

    Regards,
    Dean.
  • 0 in reply to Dean Banerjee
    Prodigy 240 points

    Hey Dean,

    1) What do you mean by PLL normalized 1/f noise.in your earlier message.

    2) What determines the Integration limit. Is it the PLL Loop Bandwidth or the application like SERDES, SONET, etc..

    3)  You mentioned in you reply the following:

    I think that what you are saying is that for 12.5 GHz, you get better jitter when you lock it up to a PLL, which is what one would expect. However, this depends on your integration limit. If you use 12.5 kHz, then it makes sense. However, I do wonder if this is the right integration limit, or you should have something much higher. If it should be somethign much higher, then you will find that locking it to a PLL does not help.

    Can you please explain why if Integration BW is higher then why locking into a PLL does not help as stated above by you

    I have done a standalone VCO in cadence for both 12.5 GHZ and 25GHZ frequencies. I calculate the RMS random phase jitter for both the clocks frequencies using PSS and Phase Noise analysis in cadence.

    . 25 GHZ VCO gives a better RMS random phase jitter than a 12.5 GHZ VCO   which is expected as per noise transfer function of VCO. I have not yet designed my full PLL. I have PFD, CP and VCO in progress. Then divider  etc.

    regards

    -pankaj

  • 0 in reply to Pankaj Chugh
    TI__Mastermind 28021 points
    Pankaj,

    1) The PLL 1/f noise changes at 10 dB/decade and dominates the PLL noise (over the figure of merit) at closer offssets. This metric is normalized to 10 kHz offset frequency and 1 GHz output frequency.

    2) The integration limit is appliation specific. For instance, in some cases the upper limit is (1/BitPeriod) and the upper limit is (1/FramePeriod). In other words, any noise changing faster than one bit period will be not seen by the system and if the system does some kind of resync every frame period, then any variation lower than that would not matter. But the lower limit can also be set by a carrier recovery loop or several other factors.

    3) Think of it this way. Assume the loop filter to be brick wall (although it isn't) and assume any PLL noise past the loop bandwidth is completely attenuated and any PLL noise before loop badnwidth offset passes right through. Also any VCO noise below loop bandwidth is completely attenuated and any noise past loop bandwidth passes right through. Then the optimal loop bandwidth would be the offset freuqency where the PLL and VCO noise cross. Suppose this frequency is 100 kHz. In this case, you make a 100 kHz loop bandwidth. Now if your lower integration limit was 2 GHz, then you see the same jitter for locked and unlocked PLL. On the other hand, if hte lower integration limit is 12 kHz, then locked and unlocked do matter. As a rule of thumb, maybe one coudl say that if the lower integration limit is >5X PLL loop Bandwidth, then locked vs. unlocked don't matter much for jitter.


    In theory, higher VCO frequency implies lower jitter as Q = X/R and the reactance increases with higher frequency. If the frequency doubles, X doubles, but R doesn't, meaning 1/2 jitter. However, at some point parasiticits and other effects come into play and beyond this point, the VCO jitter actually degrades when the VCO frequency is increased. This depends on the process you are modeling, but if your simulations do not account for these parasitics, then you might be deceived into thinking that 25 GHz VCO is better than 12.5 GHz VCO when in fact it could be the other way around. But I don't know about the process you are working on, so it's hard to say.


    Regards,
    Dean
  • 0 in reply to Dean Banerjee
    Prodigy 240 points

    Final Questions,

    1) How do you make the VCO noise and PLL noise cross (become equal) to get the optimal PLL Loop Bandwidth.In other words, for what PLL LOOP Bandwidth the VCO and PLL  Noise cross each other.

    2) How much should be the PLL Loop BW if PLL clock frequency is 12.5 GHZ or 25 GHZ. I believe it is the input reference frequency that matters..Frequency less than  wref/10 to greater than  wref/100 can be set as PLL Loop Bandwidth. If Wref=100MHZ then PLL loop Bandwidth will be between 10MHZ- 1MHZ. Am I correct.

    3) If integration limit is higher than PLL Loop Bandwidth then jitter does not matter as you stated

    4) If I have a 25 GBPS SERDES then what will be the Integration limit. If my Integration limit is much greater than PLL LOOP Bandwidth then jitter should not matter. Are you aware of any document or literature which talks about Integration limit based on application like SONET, SERDES etc. I am not clear about bit period and frame period.and lower limit based on carrier recovery loop. Are you talking about Clock data recovery. My PLL is in Transmitter PLL in SERDES

    Thanks for your help.

    regards

    -pankaj

  • 0 in reply to Pankaj Chugh
    TI__Mastermind 28021 points
    Pankaj,

    1) For PLLatinum Sim, if you choose "auto" for the loop bandwidth, this is the frequency it picks. Or, if you want to visualize this, go to advanced mode and choose brick wall filter. You will find by changing the loop bandwidth where these points cross. Yet another way is to choose "0 Hz loop Bandwidth" for the filter type and export the VCO phase noise. Then choose "Infinite loop badnwidth" and export the PLL noise and then you can see where they cross by graphing in excel.

    2) Define the loop badnwidth found in 1) as the "Optimal Jitter Bandwidth". This is probably what you want. However, the loop bandwidth should not exceed 1/10th of the phase detctor frequency. So if the phase detector frequency is 100 MHz, then the loop badnwidth can not exceed 10 MHz, or else you will get instability and discrete sampling effects. But you could choose lower than 1 MHz.

    3) If the lower integration limit is much higher than the "Optimal Jitter Bandwidth", then you are just counting on your VCO and the PLL loop badnwidth does not really matter.

    4) I don't know this, I'm not that familar with this. I don't have a formal document, but rather things I have heard here and there about lower integration limits.

    Regards,
    Dean
  • 0 in reply to Dean Banerjee
    Prodigy 240 points

    Thanks Dean for your help. You might want to include a chapter on lower integration limit in your PLL Book. Just a suggestion. Most of the people don't know what the lower Integration limit should be.

    Would it be possible for you to find out from TI's SERDES designers about the lower integration limit for 25/28GBPS SERDES.

    My questions have been answered satisfactorily.