WEBENCH® Tools/LMK04828BEVM: not getting PLL lock

Ron Breding

Part Number: LMK04828BEVM

Tool/software: WEBENCH® Design Tools

have a similar issue using the 128MHz output from a LMK04828BEVM to be the CLKIN1* input to a 2nd LMK04828BEVM in order to generate two LVDS outputs at frequencies 350MHz and 490MHz. Should I also use the on-board 122.88MHz oscillator so as to have the PLLs form a stable closure? The clock design tool doesn’t clearly show the use of this input as there is only one input clock in the upper left of the GUI window.

Attached is my setup using the clock design tool that won't lock either PLL. I've tried suing the linked Webbench Clock architect tool with the NSC Clock design Tool and can't get the two to agree. The Webbench tool doesn't give me the PLL1 R and N dividers or the PLL 2 R, N, and N Pre dividers that are need to be set in the TICS Pro tool.

LMK04828-dual-loop, 128 MHz to 122.88 MHz to 2450 MHz to 350 MHz and 490 MHz.txt

over 6 years ago

0 Rob Rodrigues over 6 years ago

TI__Mastermind 19780 points

Hi Ron,

Do you have a jitter performance requirement of the 350MHz and 490 MHz LVDS outputs you are trying to generate?

One thing I see in your config is that the VCXO frequency is 306.25. If you are using the onboard 122.88MHz VCXO, this will never lock.

I have updated the config file to work with PLL1R = 250, PLL1N = 240 to get 122.88MHz for the VCXO.

PLL2 R = 1536, PLL2 Ntotal = 30625 (Pre-N = 5, N = 6125)

I got these numbers using the LCM Calculator here:

Please let me know if this helps.

Fullscreen 3108.LMK04828-dual-loop, 128 MHz to 122.88 MHz to 2450 MHz to 350 MHz and 490 MHz_rdr.txt Download

[SETUP]
ADDRESS=888
CLOCK=8
DATA=4
LE=2
PART=LMK04828B
IFACE=SPI
ADDRESS_I2C=0x0

[PINS]
PINNAME00=SYNC
LOCATION00=7
PINVALUE00=False
PINNAME01=CLKin0_SEL
LOCATION01=0
PINVALUE01=False
PINNAME02=RESET
LOCATION02=3
PINVALUE02=False

[MODES]
NAME00=R0 (INIT)
VALUE00=144
NAME01=R0
VALUE01=16
NAME02=R2
VALUE02=512
NAME03=R3
VALUE03=774
NAME04=R4
VALUE04=1232
NAME05=R5
VALUE05=1371
NAME06=R6
VALUE06=1536
NAME07=R12
VALUE07=3153
NAME08=R13
VALUE08=3332
NAME09=R256
VALUE09=65543
NAME10=R257
VALUE10=65877
NAME11=R258
VALUE11=66133
NAME12=R259
VALUE12=66305
NAME13=R260
VALUE13=66562
NAME14=R261
VALUE14=66816
NAME15=R262
VALUE15=67312
NAME16=R263
VALUE16=67345
NAME17=R264
VALUE17=67589
NAME18=R265
VALUE18=67925
NAME19=R266
VALUE19=68181
NAME20=R267
VALUE20=68352
NAME21=R268
VALUE21=68610
NAME22=R269
VALUE22=68864
NAME23=R270
VALUE23=69233
NAME24=R271
VALUE24=69377
NAME25=R272
VALUE25=69640
NAME26=R273
VALUE26=69973
NAME27=R274
VALUE27=70229
NAME28=R275
VALUE28=70400
NAME29=R276
VALUE29=70658
NAME30=R277
VALUE30=70912
NAME31=R278
VALUE31=71417
NAME32=R279
VALUE32=71424
NAME33=R280
VALUE33=71704
NAME34=R281
VALUE34=72021
NAME35=R282
VALUE35=72277
NAME36=R283
VALUE36=72448
NAME37=R284
VALUE37=72706
NAME38=R285
VALUE38=72960
NAME39=R286
VALUE39=73337
NAME40=R287
VALUE40=73523
NAME41=R288
VALUE41=73736
NAME42=R289
VALUE42=74069
NAME43=R290
VALUE43=74325
NAME44=R291
VALUE44=74496
NAME45=R292
VALUE45=74754
NAME46=R293
VALUE46=75008
NAME47=R294
VALUE47=75513
NAME48=R295
VALUE48=75520
NAME49=R296
VALUE49=75784
NAME50=R297
VALUE50=76117
NAME51=R298
VALUE51=76373
NAME52=R299
VALUE52=76544
NAME53=R300
VALUE53=76802
NAME54=R301
VALUE54=77056
NAME55=R302
VALUE55=77561
NAME56=R303
VALUE56=77568
NAME57=R304
VALUE57=77830
NAME58=R305
VALUE58=78165
NAME59=R306
VALUE59=78421
NAME60=R307
VALUE60=78592
NAME61=R308
VALUE61=78850
NAME62=R309
VALUE62=79104
NAME63=R310
VALUE63=79481
NAME64=R311
VALUE64=79667
NAME65=R312
VALUE65=79872
NAME66=R313
VALUE66=80128
NAME67=R314
VALUE67=80396
NAME68=R315
VALUE68=80640
NAME69=R316
VALUE69=80896
NAME70=R317
VALUE70=81160
NAME71=R318
VALUE71=81411
NAME72=R319
VALUE72=81664
NAME73=R320
VALUE73=81933
NAME74=R321
VALUE74=82176
NAME75=R322
VALUE75=82432
NAME76=R323
VALUE76=82705
NAME77=R324
VALUE77=83147
NAME78=R325
VALUE78=83327
NAME79=R326
VALUE79=83472
NAME80=R327
VALUE80=83730
NAME81=R328
VALUE81=83970
NAME82=R329
VALUE82=84290
NAME83=R330
VALUE83=84482
NAME84=R331
VALUE84=84758
NAME85=R332
VALUE85=84992
NAME86=R333
VALUE86=85248
NAME87=R334
VALUE87=85696
NAME88=R335
VALUE88=85887
NAME89=R336
VALUE89=86019
NAME90=R337
VALUE90=86274
NAME91=R338
VALUE91=86528
NAME92=R339
VALUE92=86784
NAME93=R340
VALUE93=87160
NAME94=R341
VALUE94=87296
NAME95=R342
VALUE95=87802
NAME96=R343
VALUE96=87808
NAME97=R344
VALUE97=88214
NAME98=R345
VALUE98=88320
NAME99=R346
VALUE99=88816
NAME100=R347
VALUE100=89055
NAME101=R348
VALUE101=89120
NAME102=R349
VALUE102=89344
NAME103=R350
VALUE103=89600
NAME104=R351
VALUE104=89867
NAME105=R352
VALUE105=90118
NAME106=R353
VALUE106=90368
NAME107=R354
VALUE107=90788
NAME108=R355
VALUE108=90880
NAME109=R356
VALUE109=91136
NAME110=R357
VALUE110=91393
NAME111=R369
VALUE111=94634
NAME112=R370
VALUE112=94722
NAME113=R380
VALUE113=97301
NAME114=R381
VALUE114=97587
NAME115=R358
VALUE115=91648
NAME116=R359
VALUE116=91927
NAME117=R360
VALUE117=92397
NAME118=R361
VALUE118=92505
NAME119=R362
VALUE119=92704
NAME120=R363
VALUE120=92928
NAME121=R364
VALUE121=93184
NAME122=R365
VALUE122=93440
NAME123=R366
VALUE123=93715
NAME124=R371
VALUE124=94976
NAME125=R8189
VALUE125=2096384
NAME126=R8190
VALUE126=2096640
NAME127=R8191
VALUE127=2096979

[FLEX]
bSetFeedback_CLKin1=CLKin1 (External)
bSetFeedback_DCLKout6=DCLKout6
bSetFeedback_DCLKout8=DCLKout8
bSetFeedback_SYSREFDIV=SYSREF divider
bSetJESD204B_Continuous=Continuous
bSetJESD204B_NoJESD204B_withoutSYSREFDivider=No JESD204B
bSetJESD204B_Pulser=Pulser
bSetJESD204B_Reclocked=Reclocked
bSetJESD204B_SYSREFREQ=SYSREF Request
bSetMode_Distribution=Set Distribution
bSetMode_DualLoop=Set Dual Loop
bSetMode_DualLoop0DelayCascaded=Set Dual Loop 0-Delay Cascaded
bSetMode_DualLoop0DelayNested=Set Dual Loop 0-Delay Nested
bSetMode_SingleLoop=Set Single Loop
bSetMode_SingleLoop0Delay=Set Single Loop 0-Delay
bSet_CLKin0toOff=CLKin0 Off
bSet_CLKin0toPLL1=CLKin0 drives PLL1
bSet_CLKin0toSYSREF=CLKin0 drives SYNC/SYSREF
bSet_CLKin0toSYSREF_Direct=CLKin0 drives SYNC/SYSREF direct
bSet_CLKin1_ExternalVCO=CLKin1 drives Clock Distribution (external VCO/distribution mode)
bSet_CLKin1toOff=CLKin1 Off
bSet_CLKin1toPLL1=CLKin1 drives PLL1
bSet_CLKin2_Input=CLKin2 for PLL1
CLKDIST_FREQ=2450
CLKin0_FREQ=122.88
CLKin1_FREQ=128
CLKin2_FREQ=153.6
CLKin_SEL_AUTOPINSMODE=1
EXT_VCXO_FREQ=122.88
FB_MUX_FREQ=102.0833333333
FB_MUX_FREQ_MHz=
OSC_FREQ=122.88
OSCin_SOURCE=0
PLL1_PD_FREQ=0.512
PLL2_PD_FREQ=0.08
PLL_FBMUX_WARNING_TEXT=
PLL_WARNING_TEXT=
WARNING_TEXT_PLL1=Set CLKin1_OUT_MUX to drive PLL1
WARNING_TEXT_PLL2=
CLKDIST_FREQ=2450
SYSREF_FREQ=0.7975260417
bSYNC_DIS_AllOff=All Off
bSYNC_DIS_AllOn=All On
bSYNC_DIS_CLKOff=DC Off
bSYNC_DIS_CLKOn=DC On
bSYNC_Dividers=SYNC Dividers
bSendPulsesViaSPI=Send Pulses
bSetJESD204B_Continuous=Continuous
bSetJESD204B_Pulser=Pulser
bSetJESD204B_RX_CLKin0=CLKin0
bSetJESD204B_RX_CLKin0_Bypass=CLKin0 Bypass
bSetJESD204B_RX_Ignore=None
bSetJESD204B_RX_Reclocked=Re-Clocked
bSetJESD204B_RX_SYNCpin=SYNC Pin
bSetJESD204B_SYSREFREQ=SYSREF Request
bSetSYNC_Normal=Normal
stSYSREF_CLR_WARNING=
CLKDIST_FREQ=2450
CLKout0_FREQ=350
CLKout10_FREQ=306.25
CLKout11_FREQ=306.25
CLKout12_FREQ=408.3333333333
CLKout13_FREQ=408.3333333333
CLKout1_FREQ=350
CLKout2_FREQ=490
CLKout3_FREQ=490
CLKout4_FREQ=306.25
CLKout5_FREQ=306.25
CLKout6_FREQ=102.0833333333
CLKout7_FREQ=102.0833333333
CLKout8_FREQ=306.25
CLKout9_FREQ=306.25
OSCout_FREQ=306.25
SDCLKout11_TEXT=
SDCLKout13_TEXT=
SDCLKout1_TEXT=
SDCLKout3_TEXT=
SDCLKout5_TEXT=
SDCLKout7_TEXT=
SDCLKout9_TEXT=
SYSREF_FREQ=0.7975260417

Best Regards,

0 Ron Breding over 6 years ago in reply to Rob Rodrigues

Intellectual 585 points

So should I even be using the Webbench Clock architect tool with the NSC Clock design Tool? So far I'm 0 for two attempts at getting PLL locks. This has been very frustrating and consumed a lot of time. I assumed these tools were provided to be used to fill out the TICS Pro parameters for the LMK04828B EVM and other clock generating EVMs. This has not been my experience at all. I'll download the tool linked above, but I'm at a loss as to what TI tools to use in the future. I know the NSC Clock Design provides values, BUT it's broken. I haven't been able to set up a LMK04828B using this toolset. Hopefully, the tool linked above will work better. Thank your for your help.

0 Rob Rodrigues over 6 years ago in reply to Ron Breding

TI__Mastermind 19780 points

Hi Ron,

At this time, multiple pieces of software are used to do a full configuration and analysis of a clock distribution design. The Webbench Clock Architect tool is useful for a first pass part selection. The other features it offers can be performed easier, and with more information provided when using TICS Pro, PLLatinum Sim, and/or the Clock Design Tool.

Using multiple pieces of software is a known limitation that we are creating a plan to solve in the near future. The broad code base of these tools is one of the points causing the delay. I'd rather have to point you to 3 software tools than 1 broken tool.

TICS Pro can -

configure LMK/CDC devices

Simulate single loop and dual loop PLLs

loop filter design

PLLatinum Sim can -

Accurately simulate PLL noise performance for single loops

loop filter design and optimization

Clock Design Tool does essentially everything that TICS Pro does.

Best Regards,

0 Ron Breding over 6 years ago in reply to Rob Rodrigues

Intellectual 585 points

So using the CLock Desgin Tool and entering those parameter values for the filtes, N, and R values for a dual PLL solution has not allowed lock on either PLL1 nor PLL2. The Web Clock Architect provides great infomation on PLL lock closure but does not answer the set parameters for the N and R values. That leaves the discrepancy of the NSC Clock Design Tool and the locking of the loops. I've been trying all week on my own and have only made progress the the help of the E2E Forum discussions.

Clock & timing

Clock & timing forum

WEBENCH® Tools/LMK04828BEVM: not getting PLL lock