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LMK04610: Issue with device boot-up and locking

Part Number: LMK04610
Other Parts Discussed in Thread: LMK04616,

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Hello,

 

We are using LMK04610 and LMK04616 in our design to generate 90MHz,, 80 MHz and 105MHz frequency using 100 MHz input reference clock.

 

LMK04616   - 105 MHz

LMK04610   - 90MHz/80MHz 

 

We have designed the PLLs to operate in PLL2 only mode with the reference clock of 100MHz fed to Clkin0 port. The Oscin pins are left floating. I have attached register configuration files for your review.

 

Steps followed to configured to LMK:

1. reset pin is toggled from low to high

2. Register 0x0011 is configured with x00

3. Register 0x0000- 0x00153 is configured as per attachment

4. Register 0x0011 is configured with x01

 

The above mentioned steps are followed for configuration of the device but yet the desired output frequency is not being generated and we are unable to find out the cause for the same. The read back from the device is not happening either. Request your response at the earliest.

Regards,

Ayesha

  • Hello Ayesha,

    This appears correct from a quick look. We'll take a more detailed look this week.

    Do I understand you are using the 4 wire mode for SPI readback and status1 as the output? Can you send me a scope shot of all 4 lines during your example readback spi transaction?

    It is important to configure the inputs as differential for differential signals and single ended for single ended. I presume this has been done?

    73,
    Timothy
  • Hi Timothy,

    We have now changed to three wire mode where we are using the data line in SDIO mode. Will share the screen shots shortly.

    However we have probed the supplies during programming and they are stable. Also, the inputs are configured as differential. Please find the .tcs files attached.

    Also, post the reset pin is toggled, what is the expected voltage on PLL2_LDO_CAP and PLL2_VCO_LDO_CAP. The datasheet doesn't mention these values. We suspect the device is not getting powered up.

    Regards,

    Ayeshahttps://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/48/LMK_5F00_Design.7z.

  • Hi,

    We are able to bring up the LMK04610 and LMK04616. But the output frequencies are incorrect. Kindly request you to check the .tcs files attached on the respective EVMs if the required frequency is getting generated.

    Regards,

    Ayesha

  • Hi,

    For LMK04616 output configuration of 105MHz, the output observed is 102.672 MHz and the output is drifting(in 2kHz range) and when calculated the VCO output frequency, it is 5749.632MHz which is out of the device VCO operating range. Please suggest the charge pump values for below configuration

    FIN_PLL2 FVCO PLL2_RDIV PLL2_NDIV PRESCALER INPUT MODE
    100MHz 5880MHz 10 147 4 Divider
  • PLL2 is unlocked.

    PLL2_PROP= 20 (0x007214) , PLL2_INTERGRAL_GAIN=0 (0x008000)get loop bandwidth aroung 700kHz, which is too wide for phase detect frequency 10 MHz.
    Suggest change to PLL2_PROP= 7 (0x007207) , it achieves LBW around 300kHz.
    When PLL is locked, frequency offset ppm value is the same for input and output clocks.
  • Hi,

    We tried this but it did not help. The PLL2 didn't lock with this change. The reference clock used has a stability of 0.2ppm. The drift observed is because PLL2 is not locked.

    Please specify the recommended PLL2 loop filter values for the above configuration.

    Also, do we need to follow a specific register programming sequence or do we need to re-write any registers? Please advise.

    Please let me know if the required frequencies can be checked using LMK04610/6 evaluation board? 


    Regards,
    Ayesha