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LMK04610: SYNC Mode Question

Sepeedah Zadeh
Expert 3150 points
Part Number: LMK04610


Hello team, 

We are trying to better understand SYNC mode and features with customer. 

The goal in the study is to synchronize output clocks using SYNC to an external event. Maintaining known latency between SYNC event and outgoing clocks is important in this case. Also knowing the relationship between SYNC event and outgoing clocks phase is important. Can you help with below understanding please:

  • Is SYNC event itself deterministic in phase relation to incoming clock? In other words will output clocks maintain their phase relationship to the incoming clock before/after the event?
  • Is SYNC event synchronous or asynchronous to the incoming clock?
  • Is there really no clocking going on during SYNC event or is it one of the settings (digital delay perhaps)?
  • If so what would be a “No CLKout during SYSNC” delay? Is it deterministic?
  • What was the purpose of the SYNC pin? To align clocks once upon device/system start?

Thank you!

  • 0
    TI__Mastermind 28560 points

    Hello Sepeedah,

    Sepeedah Zadeh said:
    Is SYNC event itself deterministic in phase relation to incoming clock? In other words will output clocks maintain their phase relationship to the incoming clock before/after the event?

    If 0-delay is used, then the clocks will re-align to maintain phase as before... subject to rules for 0-delay.  For example if a 100 MHz clock is used for feedback to a 10 MHz reference, then the 100 MHz clock will be deterministic, but if you also produce a 50 MHz clock, ti may not be.  You would have to feedback the 50 MHz to assure it's phase relationship in this case.

    Sepeedah Zadeh said:
    Is SYNC event synchronous or asynchronous to the incoming clock?

    My current understanding is it is asynchronous.

    Sepeedah Zadeh said:
    Is there really no clocking going on during SYNC event or is it one of the settings (digital delay perhaps)?


    /1 or bypass clocks will continue to operate.  Actually, this is a bit confusing because the text of 9.3.2.3 states clocks with /1 or bypass are not gated, but the image in figure 32 appears to show they are gated.  I'd have to confirm.

    Sepeedah Zadeh said:
    If so what would be a “No CLKout during SYSNC” delay? Is it deterministic?

    For the clock which are gated, they are asynchronously turned off on SYNC assertion.

    Sepeedah Zadeh said:
    What was the purpose of the SYNC pin? To align clocks once upon device/system start?

    I think the primary purpose is to allow the user to cause all clocks to have deterministic timing to one another, that timing being set by the static digital delay values.  However you can see in the JESD204B Multi-Device Synchronization Using LMK0461x, SNAU222 application note that SYNC is used to reset dividers.

    Please refer to the app note JESD204B Multi-Device Synchronization Using LMK0461x, 

    Can you tell me more about what you are trying to achieve?

    73,
    Timothy

  • 0 in reply to Timothy T
    Prodigy 200 points

    Hi Timothy,

    Sepeedah has posted this upon the request from us. In other words these questions came from us.

    Here is what we are trying to do:

    We are planning a system of multiple JESD204B DACs and ADCs and LMK04610 device that will by synchronized to much slower but irregular in frequency event. Think of it as once in a while at a random time the system will get a synchronicity trigger (synchronous to the incoming clock to LMK04610 device). It is the nature of our system such that we need deterministic and repeatable latency from that trigger event to the SYSREF output to all the devices.

    In retrospect I think it will be more useful to us to use SYNC pin as clock sync upon startup only and then reconfigure it as a SYSREF issuer.

    Follow up question:

    If SYNC is reconfigured as a pulsed SYSREF issuer with number of pulses being issued 1 and 0 digital delay, what is the practical delay between assertion/release of SYNC and SYSREF being issued?

    Incoming clock is 125Mhz, outgoing clock 750Mhz, SYSREF outgoing frequency is set to 7.8125Mhz.

    See image below.

     

  • 0 in reply to aleksey makasarashvili
    TI__Mastermind 28560 points
    Ok thanks, what sort of timeline are you looking for this information by? Was the app note of any help to you?

    73,
    Timothy
  • 0 in reply to Timothy T
    Prodigy 200 points
    Timothy,

    Thank you for your help. I was hoping this was an undocumented or overlooked in the datasheet explanation. In general what is the minimum latency between getting SYSREF request and actual SYSREF pulses coming out? And how is it varied between devices? I seek understanding on how device works with aspect to SYSREF. The particular example that I have given you is just an example. I place the least priority on the specific answer for it. But in general we have a week or so to before we have to know the answer on how SYSREF works.
  • 0 in reply to aleksey makasarashvili
    TI__Mastermind 28560 points
    Hello Aleksey,

    Ok thanks. I or a co-worker will post more info as we investigate the info we have on this.

    73,
    Timothy