LMK04828: Deterministic Latency with SYNC and SYSREF

Jhoneldrick Millares

Part Number: LMK04828
Other Parts Discussed in Thread: ADS54J66, DAC38J84,

Does performing SYNC via toggling the SYNC_POL pin need to be synchronous to an external clock?

I have an DAC38J84 clocked by an LMK04828B and an ADS54J66 clocked by an LMK04828B. The latter LMK04828B is kept synchronous to the former via OSCout feeding into its PLL1 network.

Upon initialization, I follow the Setup of Sysref Example in the LMK04828B datasheet, but do not achieve deterministic latency on when my sample data is available to my FPGA. The start of the sample drifts up to ~80 clock cycles (at a data rate of 245.76 MSPS, this translates to ~333ns of variation). One of the problem areas I have identified is the Syncing of the clock dividers, since this is initiated by a SPI write and is not necessarily synchronous to the sample clock.

over 6 years ago

0 Noel Fung over 6 years ago

TI__Guru** 109930 points

Hi Jhoneldrick,

We have assigned people to help you, stay tuned for another update. Thank you for your patience.

0 Timothy T over 6 years ago

TI__Mastermind 28560 points

Hello Jhoneldrick,

SYNC_POL toggling does not by itself need to be synchronous to an external clock to get all the clocks of a single LMK04828 aligned with each other.

I'm still a bit unclear about your clocking setup. For example is the FPGA clocked by the LMK4828 with ADC or DAC. When you refer to start of sample, you are referring to the SYSREF? What is your SYSREF frequency?

When you say that your are keeping the latter LMK04828B synchronous to the first LMK04828 via OSCout feeding into it's PLL1 network. Are you using 0-delay on one or both devices? I think you need to use 0-delay for 2nd loop of first PLL (cascaded or nested+cascaded), and 0-delay for 1st PLL of latter LMK04828 (if not simply nested+cascaded again).

If you want to send SYSREF out on both the DAC LMK04828 and ADC LMK04828 at the same time, I recommend requesting the SYSREF on the first device, then distributing the SYSREF through the second device by re-clocking the SYSREF to second device through CLKin0 path through the D-flip flop.

Do you have a PCB designed you are doing this work on, or is this EVM's connected together?

73,
Timothy

0 Jhoneldrick Millares over 6 years ago in reply to Timothy T

Prodigy 140 points

Hi Timothy,

Thank you for the in-depth reply.

First, to answer your questions:

Here is a diagram of my clocking setup.

There are two JESD204B Blocks on the FPGA that are each clocked by the LMK04828B for their respective link partner.

This diagram also illustrates the LMK04828Bs' shared clock scheme.

The Secondary LMK operates in Cascaded 0-Delay. To clarify, its PLL1 uses the input at CLKin1 as a reference for OscIn.

The Primary LMK outputs on OscOut a Buffered OscIn. There is no reference for PLL1 for the Primary LMK.

Both LMKs use the CRYSTEK CVHD-950 as their VCXO as demonstrated in the EVMs for both parts with the appropriate feedback network through CPout1.

My sampling rate is 245.76 MSPS. With LMFS = 2441, K = 5 for both ADC and DAC, this translates to a line rate of 9.8304 Gbps. Thus the device clock I provide to the FPGA is 245.76 MHz, and the appropriate maximum SYSREF frequency is 9.8304 Gbps / (10 * F * K) = 49.152 MHz. Since I can divide this by any positive integer, I chose to divide this by 64 such that my SYSREF frequency is 0.768 MHz.

When I say "start of sample" I mean that when I begin the start of Transmission and Reception on the FPGA (which are simultaneous), the time that I receive the first sample on the FPGA data stream can vary.For example, at a sampling rate of 245.76 MSPS, imagine that I nominally receive the first sample at cycle 191. Upon a power cycle, I can repeat the same procedure but this time receive the first sample at cycle 194. 3 cycle = 12.2ns of difference.

Finally, I have a PCB designed. Unfortunately, CLKin0 is not connected and thus cannot redistribute the first SYSREF.

Follow Up Questions:

1. How should the Primary LMK operate with respect to 0-Delay mode? Since its PLL1 has no reference, is this a problem?

2. My assumption is that since the secondary LMK PLL1 is locked to to the OSCout of the primary LMK, there should be a determinsitc phase relationship between all of their output clocks and sysrefs. Is this reasonable?

3. How can I ensure deterministic SYSREF for both ADC and DAC without a re-clocked sysref scheme? Would it be sufficient to request "SYNC/SYSREF_REQ" (aka toggle the pin) simultaneously for both LMKs?

4. What is the proper boot sequence for my scenario? Currently I am programming the Primary LMK, then the DAC, then the Secondary LMK, then the ADC. Should I reset each LMK's dividers with SYNC_POL and then use a pulser + sysref_req combination to enable the suggestion in question 3?

Appreciate your time and look forward to your reply.

Best,

Eldrick

0 Jhoneldrick Millares over 6 years ago in reply to Timothy T

Prodigy 140 points

Just wanted to bump this question since it has been updated with answers to your questions.

0 Timothy T over 6 years ago in reply to Jhoneldrick Millares

TI__Mastermind 28560 points

Jhoneldrick Millares said:
1. How should the Primary LMK operate with respect to 0-Delay mode? Since its PLL1 has no reference, is this a problem?

Are you using an XO to OSCin of primary LMK? If so then the frequency accuracy of your outputs will be set by this XO. It is not a problem to operate in single loop mode bypassing PLL1. The frequency & quality of this reference will also set phase noise performance of your outputs. One advantage of using a dual loop PLL is the ability to phase lock to a low frequency reference, like 10 MHz, but then use a higher frequency VCXO as reference to PLL2 to maximize performance.

Please refer to the Choosing Loop Bandwidths for PLLs presentation in the files section of the clock & timing E2E.

Jhoneldrick Millares said:
2. My assumption is that since the secondary LMK PLL1 is locked to to the OSCout of the primary LMK, there should be a determinsitc phase relationship between all of their output clocks and sysrefs. Is this reasonable?

They are phase locked (which results in frequency lock). But phase information is lost. When locking a PLL. Given a 245.76 MHz reference for example. PLL2 will /2 to 122.88 MHz phase detector then * 24 to 2949.12 MHz. To get 245.76 MHz VCO is divided by 12. So there will be 12 different phase relationships from reference to output. Anytime you have a divide which is not synchronized it introduces possible phase error from one lock to the next. Even the PLL R = /2 introduces non-determinism, doesn't matter given phase from 245.76 MHz in my example.

> One way to fix this is 0-delay. This would take a 245.76 MHz output, do a final /2 (PLL2 N) to match the phase detector frequency and allow input to output phase determinism.

The catch is that generally 0-delay will only keep signal in phase which have a GCD(input frequency, output frequency) = input frequency. This becomes an issue for if you have a lower frequency SYSREF you want to be phase aligned by 0-delay. Now there are ways to make these align by using a REFERENCE as SYSREF frequency, then operating on 0-delay mode with the SYSREF frequency as feedback.

> If you pick an XO frequency to Primary LMK04828 OSCin as SYSREF frequency, then you could have alignment between the two devices when operating in 0-delay mode.

Jhoneldrick Millares said:
3. How can I ensure deterministic SYSREF for both ADC and DAC without a re-clocked sysref scheme? Would it be sufficient to request "SYNC/SYSREF_REQ" (aka toggle the pin) simultaneously for both LMKs?

I don't have details for setup/hold or possible timing requirements for doing this. It is theoretically possible... and if you do it in lab, you will probably find it works. But over temp, voltage, and process this is where setup and hold timing become important. Note using CLKin0 is best for timing variation.

When you say you need deterministic SYSREF for both ADC and DAC above, from JESD204B it doesn't matter when the SYSREF arrives at target JESD204B device provided the SYSREF comes on a period consistent with the SYSREF frequency. So using the scheme I suggested above of 0-delay with reference frequency = SYSREF frequency you can have deterministic phase of SYSREF from power-up to power-up between primary and secondary LMK04828 and there are no SYNC timing concerns. If you don't need deterministic SYSREF phase between primary and secondary, you don't need to worry about 0-delay. If you require SYSREF to occur at the exact same moment (JESD204B doesn't require it) - then you will have to try with the SYNC programming at the same time... but if you need this to be robust, you'd have to consider other ways to connect the boards.

73,
Timothy

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LMK04828: Deterministic Latency with SYNC and SYSREF