Hi
For our board using Xillinx RFSOC we use Xillinx reference design , using LMK04208 as RF PLL Clock.
We are using Crystek CVHD-950-125.000 VCXO as 125Mhz clock source (OSCIN) will the output are 125Mhz and 1Ghz.
This is our register config:
R0 (INIT) 0x00160040
R0 0x00140300
R1 0x00140301
R2 0x00140062
R3 0x80140603
R4 0x00140304
R5 0x80140185
R6 0x01100006
R7 0x01300007
R8 0x04010008
R9 0x55555549
R10 0x9102410A
R11 0x0401100B
R12 0x1B0C006C
R13 0x2302826D
R14 0x0200000E
R15 0x8000800F
R16 0xC1550410
R24 0x00000058
R25 0x02C9C419
R26 0xAFA8001A
R27 0x10001E1B
R28 0x00201E1C
R29 0x0180019D
R30 0x0200019E
R31 0x003F001F
Which is base on xillinx config
Could you please help us to understand that this config generate the lower jitter with the input/output levels we use?
Thanks
Oded
