Other Parts Discussed in Thread: CODELOADER
[This is a tools question, but I couldn't tell which of the tools in the pulldown list it applies to]
Hi,
In our JESD204B Subclass-1 system, the LMK04828 is replicating a 148.5MHz tone on CLKin1 to each of several clock outputs.
All of our programming has been direct, based on understanding the part's function, rather than relying on CodeLoader.
The Device and SYSREF clock output blocks appear to be functioning correctly: Frequency ratios match the divisor ratios exactly.
However, PLL1 isn't locking (that's a separate story).
The output clocks are sufficiently clean for the FPGA transceiver PLLs to lock, but perhaps that's more a testament to the robustness of the FPGA PLLs than to the stability of reflck.
The high-slew-rate, low-jitter input signal on CLKin1 is received by LMK04828 from a SiL5356.
For sanity checking, we're trying to operate the LMK04828 in distribution mode, bypassing the PLLs.
Although distribution mode of this low frequency relinquishes the ability to adjust relative phases of the device clocks, we expect to observe basic function.
Unfortunately, no device clocks are evident.
The documentation on distribution mode is scant.
It looks like the forums direct us to go purchase TICOpro.
I've installed CodeLoader now and I can see that it does not provide for distribution mode. It appears that the device clock frequencies are calculated incorrectly based on the PLL2 parameters even when VCO mux selects Fin.
Is there any way to perform the exercise we have in mind w/out going through a cycle of "submit a request to purchase design software to assist your engineers in enabling the company's substantial investment in TI converters and clock chips?
Hopeful thanks --todd
