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LMK04610: Output fast lock configuration

Jeff Xie
Intellectual 1780 points
Part Number: LMK04610
Other Parts Discussed in Thread: LMK04828

Hi team,

Customer want to achieve fast lock when there is a input. From the spectrum analyzer below, when LMK04610 is locked in 122.88 MHz LMK04610 output clock 122.88 MHz, the phase of the REF CLK clock relative to PLL1 is still changing, and it takes about 5 seconds to be relatively stable.

1. Can I use PLL fast lock function in this application?

2. Why we need 5 seconds to lock compared to LMK04828 

3. When I increase lockdec cyc-cnt, the lock time decrease, can I use this?

4 Figure 2 is the best case I tried to get lowest phase shift, any way to improve it?

Thanks.

  • 0
    TI__Guru** 107290 points
    Hi Jeff,

    How fast do you want it to lock to the input clock?
    Please note that the loop bandwidth of PLL1 is very small, the lock time of PLL1 is going to be very long. In theory, the analog lock time of a PLL is approx. equal to 4/loop bandwidth. For a 20Hz loop bandwidth, the lock time is 200ms. However, if fpd >> loop bandwidth, cycle slip will happen and this will dramatically affect the lock time. In this case, I believe the fpd is over 1MHz, so cycle slip will occur. As such, I am not surprise that the lock time is a few seconds. The same thing will happen in LMK04828.
  • 0 in reply to Noel Fung
    TI__Intellectual 1780 points
    Actually customer care about the phase drift between input and output. A stable phase difference is needed. In that means, I need to increase loop bandwidth and decrease fpd to increase performance?

    Also I want to know below option can help decrease cycle slip.
    1. PLL fast lock function
    2 Increae lockdec cyc-cnt
  • 0 in reply to Jeff Xie
    TI__Genius 9920 points
    To increase lockdec cyc-cnt can avoid reporting false locked status before loop is stable . Please attach your TICS Pro .tcs configuration file. We can save or load the . tcs by TICS Pro, and check which register could be optimized.