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SPI communication between ds90ub947 and ds94ub940

user5063720
Prodigy 10 points


TI，

At present, we have a project using your 947/940 scheme. We also want to use the SPI communication mechanism between 947/940 to transmit upgraded data packets. I see that the chapter SPI Communication in the manual only briefly introduces the configuration enabled deserializer - HSCC_MODE (0x43 [2:0]) register, without detailed case introduction. Would you like to know if there are any relevant instructions?

What I mean by sending upgraded data packets here is: for example, a zip compressed packet, how can I send it through the spi of 947 and receive it at 940?

  • 0
    TI__Expert 5480 points
    Hi Erhuo,

    Some general guidelines on SPI forward channel config of the 947 down below. I am contacting a team member to see if you can send upgraded data packets and how to receive on 940. Please be patient.

    0X43 [2:0] 100 NORMAL, 110 HighSpeed. Enable SPI forward channel

    SPI tiiming control. program set up and hold times for data to SPI clk. sets the min SPI clock pulse width values
    0x60 [7:4] SPI Hold.
    0x60 [3:0] SPI Setup.
    0x61 [3:0] SPI Delay from slave select low to initial data timing

    SPI configuration. may control polarity of SPI clock. can be configured seperate at SER nd DES
    0x62 [7] SPI master overflow detection
    0x62 [2] SPI master overflow detection flag clear
    0x62 [0] SPI clock polarity

    SPI write speed is 1/2 FPD pixel clk
    Dual_FC_SPI_max = 1 / ( (4/Video_pclk_freq) + 10ns)
    Single_FC_SPI_max = 1 / ( ( 2 / Video_pclk_freq) + 10ns)
  • 0 in reply to Sally Cheung95
    TI__Expert 5480 points
    Hi Erhuo,

    In regards to your other question, you may try and send "upgraded" packets and it may work. However, you would need to provide a definition of protocol on your end for your zip compressed packet. The SERDES pair should just capture data on the input and regenerate same data stream on output.

    You should set up register 0x43 in 940 to set the mode and clk polarity. In the D/S it states data is clocked from slave to master on SPI clk falling edge.

    Thanks,
    Sally
  • 0 in reply to Sally Cheung95
    TI__Expert 5480 points
    Hi Erhuo,

    Any other questions?

    Thanks,
    Sally