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LMK04832: SYSREF noise coupled into the clock output spectrum

Vincenzo Pizzolante
Mastermind 25306 points
Part Number: LMK04832

hi,

we are testing the LMK04832EVM and when we use SYSREF along with a clock in the same clock group, we see harmonics of SYSREF entering at the clock output spectrum.

These harmonics are eliminated by using separate groups for SYSREFs and clocks.

Would it be recommended to use different groups for SYSREFs at our design (to eliminate harmonics at clocks) or is it just a problem of the EVM due to nets proximity (cross-talks?)?

If we do separate SYSREFs from clocks, will we face problems with tuning the phase of SYSREF with respect to the clock it must align to?

Or is it preferred to pair clocks with SYSREFs?

Some details:

  • Output clock frequency 2.450GHz.
  • SYSREF frequency: 38.28125MHz.
  • Input clock: 350MHz single-ended from sinusoidal clock generator, connected to CLKIN1*.
  • All used outputs terminated to 50R loads (the one probed terminated at the Spectrum Analyzer).

We also tried to bypass the output clock divider and used CML16mA output and we saw good results so far.

We have not changed the hardware of the EVM to support the CML though.

Attaching also configuration files.

any advice is more than welcome

thanks a lot in advance

KR

Vincenzo

ADC_EVM_TI_Inquiry.zip

  • 0
    TI__Guru** 107300 points
    Hi Vincenzo,

    crosstalk is unavoidable between two adjacent clock output channels. We must use separated groups for clocks and SYSREF.
    My colleague can provide more suggestions to you, he will be back from vacation in next week.
  • 0
    TI__Mastermind 33580 points
    Hello Vincenzo,

    We have seen several cases where continuous SYSREFs crosstalk with outputs, and we do not believe this to be due to the EVM layout. It is more likely that crosstalk is coupling through the power supply connections between related clock groups, which is difficult to mitigate if clock outputs from the same output group are used to generate both the device clock and the SYSREF.

    Separating the SYSREF from the device clocks onto a separate clock group should not introduce any unique difficulties, as both signals are derived from the same VCO. If additional tuning is needed to trim the alignment of the SYSREF signal edge to the output clock transition, the SYSREF path includes both an analog and a digital delay tuning step. Our own testing suggests that a device clock on OUT0 and a SYSREF on OUT11 or OUT13 can provide much lower crosstalk, but this should be considered a starting point and there may be other configurations which crosstalk less depending on the output formats and the specific frequencies used.

    We also saw in our testing that CML outputs in general are an improvement over LVPECL for crosstalk aggressors. So overall, it sounds like you are on the right track.

    Regards,