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Phase noise performance not matching the datasheet values

Karthik M1
Prodigy 70 points
Part Number: LMX2594

Hi,

I have designed a tone generator using LMX2594. But, the phase noise performance of the tone generator is not matching the datasheet performance.

For example: For a 3.5GHz carrier at an output power of 2dBm, the phase noise performance is given below

Frequency Offset Phase Noise(dBc/Hz)
1kHz -98.34
10kHz -102.83
100kHz -105.34
1MHz -113.61

But, the datasheet performance(Page No. 12 in the LMX2594 datasheet) is given below

Frequency Offset Phase Noise(dBc/Hz)
1kHz -106.8
10kHz -117
100kHz -119.7
1MHz -130.6

What might be the reason for the degradation in the phase noise performance?

Regards,

Karthik

  • 0
    TI__Mastermind 18070 points
    Hi Karthik,

    The phase noise of PLL output is dependent on the quality of reference source. The datasheet numbers are measured using a very clean reference (100MHz Wenzel oscillator). If you use the on-board oscillator or reference pro as reference. You'll likely get ~100fs integrated jitter from 100Hz to 100MHz in integer mode. With a very clean source, you can get ~50fs as shown in the datasheet.

    Regards,
    Hao
  • 0 in reply to Hao Z
    Prodigy 70 points

    Hi Hao,

    Thank you for the response.

    I have two more queries.

    1. Do you have any documentation regarding the phase noise performance of the LMX2594EVM ?

    2. For the loop filter, initially i had used the same loop filter components as used in the LMX2594EVM schematic. But, then I changed the capacitor closest to the VCO (C4_LF) from 1.8nF to 10nF. This changed the phase noise at 1MHz offset from about -113dBc/Hz to about -120dBc/Hz. The phase noise at lower offsets by and large remained the same. What changes would you recommend so as to improve the phase noise performance at lower offset frequencies ?

    Regards,

    Karthik

  • 0 in reply to Karthik M1
    TI__Mastermind 18070 points
    Hi Karthik,

    The datasheet has several typical performance plots for phase noise. You can also use "PLLatinum sim" to simulate phase noise. The simulation matches measurement very well.

    After changing the C4_LF, what happens is that the loop bandwidth is reduced so the PLL noise and OSCin noise are better attenuated at 1MHz. That's why you see a lower phase noise. But then VCO phase noise kicks in early, so the integrated jitter actually becomes worse.

    To reduce flat PLL noise or 1/f noise, you can increase phase detector frequency.

    If you want to know more about PLL theory, you can search for "Dean Banerjee PLL book" and download a free copy.

    Regards,
    Hao
  • 0 in reply to Hao Z
    Prodigy 70 points
    Hi Hao,
    Thank you for your response. It was really helpful.
    Regards,
    Karthik