• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 21 subscribers
  • Views 299 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CDCI6214: CDCI6214: Can't get an output HCSL signal on Y1 - Y4.

user6005325
Prodigy 10 points
Part Number: CDCI6214

Hi team,

We use the CDCI6214 for Ref CLK of PCIe Gen3.

But we set it as HCSL in TICS PRO, channel 1-4  has erro different  clock output.  (Waveform see blow.)

(we set it as CML in TICS PRO, channel 1-4  has clock output.)

Please help me find where the HCSL problem .

Regards,

Abel

 

  • 0
    TI__Guru** 106760 points
    Hi There,

    I assume you are working on the EVM.
    The default hardware configuration for Y1 and Y4 are not intended for HCSL output.
    You need to modify the board in order to support HCSL output. See Table 2-2 of the EVM user's guide for details.