LMK04828: Dynamic Digital Delay operation of SYSREF_DIVIDE

Hi Tim,

One DDLYd_STEP_CNT corresponds to a single cycle of the clock distribution path frequency (the frequency fed into the SYSREF Digital Delay and Clock Divider blocks - this is selected by VCO_MUX). The operation of the DDLYd_SYSREF_EN and DDLYd_STEP_CNT is functionally equivalent to the operation of DDLYdX_EN and DDLYd_STEP_CNT, with the exception that the _CNTH and _CNTL blocks are not present on the SYSREF path so the duty cycle will always be 50% (±1 cycle for odd SYSREF Divider values). So if the SYSREF is derived from VCO1, and DDLYd_STEP_CNT = 1 step, the SYSREF clock will be delayed by one cycle of the VCO1 clock.

Setting DDLYd_SYSREF_EN = 1 will affect all SYSREF related signals that take input from the SYSREF Clock Divider. When SYSREF_CLKin0_MUX derives its input from SYSREF_MUX, the following SYNC modes are affected by DDLYd_SYSREF_EN and DDLYd_STEP_CNT: Re-clocked, Pulser, and Continuous. These same modes are also affected when SYSREF_REQ_EN = 1.

Regards,