LMK04828: Register read result right after register write

Hi Kawai,

In general if the register itself is not a "readback" type, like setting N divider value, then user should be able to read back what they wrote right away. If it is a "readback" type of register such as lock status indicator then what is read back is irrelevant to what was written. So in general we don't expect any delay between reading and writing for non-readback type registers.

In the example you mentioned, there are two variables, one is "wait some time" and the other is "write again". So I'm not sure which one is the dominant factor.  Is it that you have to read twice to get the right answer or is it that you have to wait for some time before attempting to read.

Instead of reading a single register, try "read all registers" and / or type the register field name here and hit "read". It may be just a GUI problem.

Regards,
Hao

Hi Kawai,

There is a state machine inside the IC which controls the logic for powerdowns and other settings. While there are a few features (such as global IC powerdown/reset) which are implemented asynchronously, most functions in this state machine are clocked, and the clock is usually derived from the reference clock input. It may take a few clock cycles for the system to assert conditions in updated registers. In the example you gave, R0x106 upper nibble controls some CLKout0 powerdown bits. It is possible that the state machine clock is slow enough with respect to the SPI clock that immediate readback can poll the register values before they have completely changed.

In general, we do not specify the write delay for these operations to complete, since these delays can change based on reference clock speed and are often affected by other register settings (e.g. a powerdown may be faster if some sub-blocks are already powered down). If precise delay information is required for a specific case, the delay can be measured accurately using the chip select (CS) pin signal. For example, with powerdowns:

1. Insert a sense resistor on the relevant power rail (for R0x106, Vcc12_CG0) and probe the real-time differential voltage across this resistor
2. Probe the CS line in the SPI bus
3. Probe the reference clock
4. Check the delay between communication complete and change in supply current, and quantify in reference clock cycles
5. Repeat measurement several times to ensure consistency

This method works well for register updates that yield measurable changes in output frequency, power consumption, etc.

On the other hand, if all the customer needs is to guarantee the write has completed, they can continue to poll the register until the values read match the values written. This should work for any register that is not self-clearing (such as software reset).

So to summarize:

• Some register operations are tied to the state machine clock. If the state machine clock is slow compared to the communication speed, sometimes the old value can be read back before the new value is updated.
• Precise timings for specific scenarios could be measured using the CS pin signal and looking for the expected external change (current consumption, frequency adjustment, etc)
• Reading back the values until they match the written values is straightforward for any register that is not self-clearing. Self-clearing registers like the software reset register may need other methods like the one outlined above with the CS pin signal.

Regards,