Part Number: LMK00105
Hi Team,
We have a requirement to fanout 1PPS signal into two (one FPGA and one clock synchronizer) destinations, both destinations are at 1.8V logic. So we can set the Vddo at 1.8V. But the challenging point here is, we can't assure the voltage level of 1PPS input, it may be 1.8V or 3.3V. In this scenario, how we can set Vdd (Supply for operating core and input buffer) ? Also please help to fix the biasing for the same.
Best regards,
Shibili
Hi Shibili,
You can set Vdd to 3.3V:
Which biasing are you talking about?
Regards,
Hao
By the way, the output level is not dependent on the input, it is decided only by Vddo:
So as long as input and output requirements are met separately, there should be no problem.
Regards,
Hao
Hi Shibili,
There should be no problem if all other specs for input clock are met as well, such as input common mode and voltage swing:
You can do AC coupling and use provide common mode voltage externally if they are not met.
Regards,
Hao
Hello Shibili,
Please refer to section 8.1.1 Clock Inputs of the datasheet. The common mode voltage is mentioned to help set the input bias voltage when using DC-coupled single ended configuration.
