LMX2491: RF and crystal drive requirements

Hello Hao:

Thanks for that answer.  It is good to hear that the swing is 0.5Vpp to Vcc-0.5Vpp, but it is quite easy to misinterpret that from the way the data sheet is written, since that reads like the two peaks of a swing. 

But, I still have a bit of a problem figuring out how to best drive the reference input of the LMX2491.  This is not because a cleaner like the LMK04828 might be needed.  It is because the data sheet is recommending a 50 ohm pad on the input of the reference pin, and because most crystal oscillators have a problem driving that pad and meeting the swing.  Very few could also meet the 3V/ns slew rate recommended for low noise applications like the one I am designing for.  There is also no model provided of that input that I know of. 

Let's go through the details and evidence.  The data sheet application examples show crystal oscillators directly driving a 50 ohm 6 dB T-pad feeding the reference input. A typical VCTCXO draws about 2mA bias current and is typically spec'ed to drive 10k in parallel with 15pF in clipped sine wave mode.  The 50 ohm 6dB T-pad has an impedance to ground of 86 ohms.  If +/- 1mA can be diverted in drive to this load (assuming the LMX2491 takes basically zero), the swing going into the LM2491 will be 172mVpp, so it is below the 500mV peak to peak minimum.  It is also WAY below the recommended 3V/ns (Note 1 bottom of page 5).  A clipped sine wave of 172mVpp at 50MHz has max slope of 0.027V / ns, only 1% of the recommended amount.  You cannot get to the recommended amount except by a near rail to rail near square wave. 

If the VCTCXO has a digital CMOS output, then under those conditions it is driving 86 ohms to ground on the high side of the swing.  If that CMOS output can pull 86 ohms all the way high, for example to 3.3V, then it is sourcing 38mA during that high swing.  That's a pretty heavy drive requirement--usually way past what the CMOS VCTCXO is specified to do.  For example, take a look at the Taitien TA data sheet attached.  In CMOS form it can swing 10% to 90%, but that is assuming a capacitive load of 15pF.  It is not specified to drive ANY resistance, and certainly not the 50 ohm pad shown in the data sheet. 

Some oscillators are available that can drive more power.  For example, the new Taitien TKCABLJTDD-100MHz (also attached) is a high power low noise VCTCXO ideal for use with sigma delta synthesizer IC's.  It draws as much as 40mA to get its excellent noise performance.  But, even this high power VCTCXO is only specified to drive 1k in parallel with 15pF.  It also will not drive the kind of low impedance pads TI is recommending. The only crystal oscillators I know of that are specified to drive 50 ohm loads are some of the high power ovenized oscillators. 

So, that raises the question of whether such a 50 ohm pad that is such a burden on the crystal oscillator should even be used.  The only reasons I know of for such a pad would be one of two conditions:

1. There is a 50 ohm analog amplifier input impedance on the reference input that needs a broadband match (is there?), or

2.  It is assumed the reference input is on the end of a rather long 50 ohm microstrip trace, and there is a need to prevent reflections down that line.  But, a wavelength in board at 50MHz is going to be about 3 meters long, so even if there were a fairly long line run of say 10cm, that would only be about 3% of a wavelength.  Good layout practice should be able to keep it to 1% of a wavelength. 

So, the problems arise because of the pad placed on the reference pin input and the inability of almost any lower cost/power crystal oscillator to drive it. The need for that pad, or the ability to avoid that pad, could be better understood if the input requirements on the reference pin were better explained.  For example, is that input digital, or is there an analog input there that needs a 50 ohm broadband match?  If so, can an input model be described?  The data sheet does say that if the oscillator drive is differential, it MUST be at 100 ohms differential impedance (page 9).  That is implying it is an analog input, but perhaps it is a digital input that is resistively loaded to give 50 ohms impedance per pin.  What is it?

And, is it really necessary to meet that extreme slew rate of 3nV/sec to get the best noise performance out of the part? If it is necessary, then the ONLY way that is going to be met is with a strong near square wave driver like the Texas Instruments CDCLVC1102, $1.24 at 2k Digikey.  It has pretty good additive phase noise, but if it is not good enough then there are lower noise clock buffers available.  An example is the Linear LTC6957, a part really optimized for low noise, but now we are talking some money at $4.45 at 500 Digikey.  It costs more money and burns more power than the synthesizer and crystal reference put together.  But, the LMX2491 data sheet is effectively saying that this is necessary to get the best phase noise performance.  Is it?

Thanks,

Farron

TKCABLJTDD-100.000000MHz VCTCXO Proposal spec.pdf

TAtype7X5mm.pdf

Hello Dean:

Thanks for the quick reply and on-point information. 

I looked at the LMX2581 datasheet, and did not see the information on phase noise as a function clock slew rate.  Are you sure that is the right data sheet?

I did find a nice graph in the LMX2571, page 41, showing a 5dB degradation in close-in phase noise if the reference input is driven by a typical VCTCXO instead of a higher voltage higher dv/dt source.  That is great information to have for best close in phase noise.  

Linear Tech, like TI, often recommends low impedance resistive padding or matching on reference oscillator inputs. The problem is that there is a complete mismatch there with what the crystal oscillators are specified to be able to drive.  There is a design hole here you could drive a truck through.  Either the crystal oscillators need to provide more drive, the synthesizer needs to take less drive, or the crystal has to be buffered up with a strong low noise near square wave output. 

As I mentioned above, TI does have a nice family of cost effective buffer parts, the CDCLVC11XX, whose additive phase noise is well below that of handset class VCTCXO's that really need the buffering.  You sure have a good case here for promoting the CDCLVC11XX in your synthesizer data sheets and app notes.   

It seems that for applications demanding the best close in phase noise, the smart play is to put in either the CDCLVC11XX or the even better (close in, not far out) but more expensive LTC6957 as an option.  The unloading of the brute force resistive matching at the reference input can be tried, but if it has any problems and the padding has to go back in, then the clock buffer can be stuffed to force a successful low noise solution.

An app note on this subject that closes this industry mismatch would be a good idea.

Thanks, 

Farron

Hi Dean:

OK, those are very informative graphs in the LMX2541 data sheet.  They show that the charge pump and divider noise can degrade as much as 15-19dB for lower slew rates.  I'm a pretty seasoned synthesizer designer, and I never knew it could be that bad.  Thanks for pointing that out to me. 

The 4th part of the low noise synthesizer series I was publishing in MW&RF will be turned in early next month.  The focus in that part is the practical parts available to the synthesizer designer.  After this discussion, I will be adding a section on crystal slew rate and clock buffers.

It raises a related question.  I've often seen people hitting the RF input with signal levels below the specified range.  For example, it is reported here that the LMX2491 will usually lock down to RF inputs of about -30dBm.   But, the specified range is -5 to +5dBm.  Is there a similar increase in noise when it is the RF divider being subjected to low dv/dt?  Is there any data on that? 

Thanks,

Farron