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LMX2594: LMX2594

Refael Shani
Prodigy 20 points
Part Number: LMX2594


Hi

On the last meeting we made on LMX2594 we discussed we Dean our design (See the attached email summary and attached simulations

The basic concept was :

  • Using oscillator of 40MHz (we must have this for the other parts at our system).
  • The PFD we should use is 200MHz (Dean recommendation in order to decrease the PN)

However , after internal discussion at Amimon:

  1. We understood the using a multiplication than higher than 2 (we use 5 since 40X5=200MHz) can cause a situation that the charge pump duty cycle won’t be symmetric.
  2. This why the recommendation is to work with PFD of 80 MHz

What do you think about this?

 

Our requirements:

  1. We should support frequency range between 10.8 GHz-13GHz (this is our LO, the VCO should be VCO4, VCO5 and VCO6 according to the freq range)
  2. DSB PN should be > 45dB
  3. Most of the time we will work with power setting 50
  4. Lock time <30usec

RE Call LMX2594 support for AMIMON.msg

  • 0
    TI__Mastermind 28021 points
    Refael,

    The input multiplier does allow the higher phase detector frequency, but it also degrades the PLL figure of merit. Using the x2 multiplier degrades the PLL figure of merit by 1 dB, but there is a net benefit because there is a 3 dB benefit for a higher phase detector frequency. So this is a net 2 dB benefit. The x2 multiplier creates a very non-50% duty cycle, so you can not use that in conjunction with the programmable multiplier (MULT)

    The programmable multiplier (MULT) degrades the figure of merit by about 9 dB. So if you use x5, then your figure of merit degrades 9 dB, but there is a net 10*log(5) = 7 dB. So the overall impact is a 2 dB degradation in phase noise.

    So in summary, if the goal was best phase noise, one would think the 80 MHz phase detector would be optimal. However, there are two other considerations. Firstly, if your 40 MHz input reference is not very clean, the noise of this might dominate over the PLL noise. Secondly, you want to keep the capacitor closest to Vtune line at least 1.5 nF. If not, the VCO phase noise will degrade. So one runs into the limitation that you want side loop bandwidth, but the bandiwdth gets restricted by this constraint, leading to narrower loop bandwidth, which leads to VCO phase noise cropping inside the loop badnwidth, which is higher phase noise. So in summary, if I recommended the x5, it was likely to get around this constraint and perhaps because the input reference you had was dominating PLL phase noise anyways.

    Regards,
    Dean