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LMX2595EVM: IBS

Pradeep Kumar68
Intellectual 420 points

Part Number: LMX2595EVM
Other Parts Discussed in Thread: LMX2594, PLLATINUMSIM-SW, LMX2595

Hi Ti,

We need to generate 0.5 to 18 GHz RF signal from LMX2595EVM with loop bandwidth of 280KHz, 100 MHz Ref in and 200MHz PFD. Our Frequency output step size is 1MHz. Also we need to achieve 100 dBc @ 100 KHz offset phase noise

When we check the output in non integer configuration(like 4001MHz or 17999MHz and many more),we are getting integer boundary spurs. 

By reducing charge pump we are able to reduce this IBS spur but it is degrading the phase noise at higher frequencies. So we need to operate at 15mA charge pump current and 200 MHz PFD only.

Our output is tunable in 0.5 to 18 GHz band in 200us switching speed. So we cannot keep changing the input multiplier and divider to reduce the IBS spurs.

Is there any other solution is reduce this IBS spurs.

  • 0
    TI__Mastermind 28031 points
    Pradeep,

    The LMX2594 EVM default filter was designed for optimal jitter in integer mode. However, if you use fractional mode, a narrower loop bandwidth may be required. For integer boundary spurs, there are these mitigation techniques:

    1. Change the input multiplier
    2. Change MASH_SEED
    3. Change MASH_ORDER
    4. Optimize loop filter
    5. Ensure input reference has good slew rate.

    For items 1,2, and 3, the first thing I would do is try our PLLatinum Sim tool at ti.com/tool/PLLATINUMSIM-SW. This will simulate the spurs and their root mechanisms. It models the programmable input multipler noise, MASH_SEED impact, MASH_ORDER, and designs and simulates the loop filter.

    For instance, you can change the input multiplier, but this does add lot of PLL phase noise, so be aware of this.

    The MASH_SEED also can impact the spur. The optimal seed value is specific to every fraction and PLLatinum Sim can predict this. Now this is 200 different values for MASH_SEED, but maybe you could just do it for the 10 worst case fractions.

    The modulator order can also impact the spur level as well

    PLLatinum Sim also is a very powerful tool for loop filter design that can help really get the most optimized filter.



    Also, sometimes the integer boundary spur can be caused by crosstalk that goes around the loop and if this is the case, reducing the loop bandwidth does not help. For diagnostic purposes, try reducing the charge pump gain from 15 mA to 12 mA to 9 mA to 6 mA to 3 mA. You might find that initially reducing the charge pump current improves the spurs but then beyond a point it helps no longer; this is likely because the spur at this point is crosstalking around the loop filter. PLLatinum Sim in advanced feature level mode shows the mechanism, one such one being Fout%Fosc. If this is the dominant mechanism, then improving hte slew rate actually can reduce the spurs.

    Regards,
    Dean
  • 0 in reply to Dean Banerjee
    Intellectual 420 points

    HI Dean,

    Thanks for the reply.

    I tried with changing the PFD frequencies, it did help in reducing IBS spur by 10dB. But in the mean time it is degrading the phase noise by 6dB. So how can we optimize this. 

    Also I am seeing strong IBS at 15001,15002 and 15003MHz with 100MHz ref in. This IBS is not at all reducing for any settings. Can you please check and tell if any thing we are missing here?

    Thanks and Regards,

    Pradeep

  • 0 in reply to Pradeep Kumar68
    TI__Mastermind 28031 points
    Pradeep,

    For the LMX2594, the phase detetor typically does not directly impact the integer boundary spurs.

    What I think you are seeing is that by reducing the phase detector frequeny, you are reducing the loop bandwidth, and it is this lower loop bandwidth that is causing the reduction in spurs.

    Regads,
    Dean
  • 0 in reply to Dean Banerjee
    Intellectual 420 points

    Hi Dean,

    So you mean to say, if we adjust loop bandwidth properly then we should achieve low ibs and good phase noise?

    Also I am seeing strong IBS at 15001,15002 and 15003MHz with 100MHz ref in. This IBS is not at all reducing for any settings. Can you please check and tell if any thing we are missing here?

    Thanks and Regards,

    Pradeep

  • 0 in reply to Pradeep Kumar68
    TI__Mastermind 28031 points
    Pradeep,

    Yes. If you reduce the loop bandwidth, this should reduce these spurs. When you reduce the charge pump current or phase detetctor frequency, this is reducing the loop badnwidth. So if the reduced loop badnwidth is what is really helping, you can also reduce it by designing for a lower loop bandwidth by changing the loop filter components while still keeping the charge pump gain and phase detector gain high. HOwever, be aware that if the loop badnwidth is too narrow, the VCO phase noise can crop inside the loop bandwidth.

    Also, are you aware of our PLLatinum Sim tool (ti.com/PLLATINUMSIM-SW). It can simulate spurs and phase noise and all these effects I am talking about.

    Regards,
    Dean
  • 0 in reply to Dean Banerjee
    Intellectual 420 points

    Hi Dean,

    We did reduced Loop filter bandwidth to 50 KHz. We calculated the values using TI platinum sim. I have attached file for your reference. With this we are getting less than -50 dBc IBS spurs for most of the frequencies. But for 15001 and 15002 MHz, IBS spur is little more around -42dBc. is there any specific reason for this??. Even with 280 KHz loop filter value, we had observed similar performance.

    50KHz LPF.zip

  • 0 in reply to Pradeep Kumar68
    TI__Mastermind 28031 points
    Pradeep,

    PLLatinum Sim is a powerful tool for understanding spurs, but there can be considerable difference between the measured and simulated spurs. Also, spurs can vary considerably over setup condition and part to part.

    In this case, I see the 500 kHz spur is predicted to be -67 dBc and the simulation suggests that it is dominated by the Fvco%Fosc mechanism. As it involves Fosc, you might find that changing the input frequency or format of the input OSCin signal may help your spurs. Ideally, spurs are best for low voltage but high slew rate signal, like LVDS.

    Simulation suggests reducing hte loop bandiwdht can improve the spur 5 dB, but that's a theoretical result. The fac that you are -50 dBc and simulation suggests -67 dBs makes me think that you might want to look ath te OSCin signal and make sure that this is not the cuase of this large descrepancy.

    Regards,
    Dean
  • 0 in reply to Dean Banerjee
    Intellectual 420 points

    Hello Dean,

    With help of 50 KHz loop bandwidth and 6mA charge pump current, we were able to reduce the IBS spurs to less than -50dBc.

    But we are getting one more strange problem. As per our requirement we need to achieve 200us lock time. We were able to achieve this specification for most of the frequencies. But whenever we change frequency to anywhere between 11900-12040 MHz we are getting 500 us lock time.

    We measured the lock time on oscilloscope by seeing the off period of the lock detect pin. I have attached the tic pro and platinum sim files for your reference.

    Please help us to understand this case.

    PLL test for spur.zip

  • 0 in reply to Pradeep Kumar68
    TI__Mastermind 28031 points

    Pradeep,

    Regarding the spurs, PLLatinum Sim predicts about -67 dBc for the integer boundary spur in your simulation, but I'm not sure how much better than -50 dBc you are seeing.  The theoretical dominant mechanism is "Fout%Fosc".  This means if your measurement is much worse, it is likely dominated by interaction with Fout and Fosc.  For this (1) Try increasing the slew rate of OSCin, (2) ensure that noise at the OSCin frequency is not coupling to the pull-up supply of Fout.

    Now as for the lock time, 11.9 - 12.1 GHz is a special frequency range in the datasheet on the bottom of page 23.  So this increased lock time is expected.

    If you do full assist, then you can eliminate it. 

    Regards,

    Dean

  • 0 in reply to Dean Banerjee
    Intellectual 420 points

    Hi Dean,

    So as per TI recommendation (VCO_SEL = 7, VCO_DACISET_STRT = 300 and VCO_CAPCTRL_STRT = 183 for all frequencies except 11.9 GHz ~ 12.1 GHz. For frequencies within 11.9 ~ 12.1 GHz, user must use VCO_SEL = 4 for proper VCO calibration.) Do we get lock time less than 200uS or we have do compulsory do fully assist VCO calibration??

    If fully assist VCO calibration is must to achieve less than 200us lock time, then what is the procedure for fully assist VCO calibration?? Datasheet does not speak about fully assist VCO calibration.

    Regards,

    Pradeep

  • 0 in reply to Pradeep Kumar68
    Intellectual 420 points

    Hi Dean,

    Any update on the above query??

    Regards,

    Pradeep

  • 0 in reply to Pradeep Kumar68
    TI__Mastermind 28031 points

    Pradeep,

    1.  If using partial assist mode, the user must use VCO_SEL=4.  HOwever, this is NOT the case for full assist.  Even though you tell partial assist to use VCO_SEL=4, most likely it will pick VCO5.

    If using partial assist for the frequency range of 11.9 - 12.1 GHz, the lock time will be slower.

    2.  Full assist VCO calibration is discussed briefly in the datasheet on table 5, page 29.  In general, the idea is first take the device and lock it.  Then read back the calibration settings of rb_VCO_SEL, rb_VCO_CAPCTRL, and rb_VCO_DACISET.  Then the next time you go to this frequency, force VCO_SEL_FORCE=1,VCO_CAPCTRL_FORCE=1,VCO_DACISET_FORCE=1, and then program these read back values into VCO_SEL,VCO_CAPCTRL, and VCO_DACISET.   

    Also, the attached document might be helpful.

    4403.Fast frequency switching full assist.pdf

    Regards,

    Dean

  • 0 in reply to Dean Banerjee
    Intellectual 420 points

    Hi Dean,

    One final clarification.

    We are using this LMX2595 PLL to generate frequencies from 500 MHz to 18000 MHz in steps of 1MHz. So while doing fully assist VCO calibration is it require to readback values for each 1MHz? or is it okay if we read it back every 5 or 10 MHz steps? So please advise on this. If I read it every 1MHz than we need to readback 17500 values, that will be a big task.

    Is this values are are device specific? or will it be same for all devices?

    And we are planning to use no assist calibration for all other frequencies expect for 11900-12100 MHz frequencies. Only when VCO frequency comes between 11900-12100MHz we shall use fully assist VCO calibration. I hope this procedure will not have any issues?

  • 0 in reply to Pradeep Kumar68
    TI__Mastermind 28031 points

    Pradeep,

    1.   For full assist calibration can be done every 5 MHz as stated in table 5, page 25 (last email I was wrong and said page 29).  Also, you only have to read up to Fvco=15 GHz.  For higher frequenies, it uses the doubler.

    2.THe readback values for the VCO calibration are device-specific;  you have to read them back and store them in an external memory

    3.  You can combine full assist and no assist for different frequency ranges.  Again, full assist is device specific and the settings for one device might not be the same for a different device.

    Regards,

    Dean

  • 0 in reply to Dean Banerjee
    Intellectual 420 points

    HI Dean,

    Thanks for your support. It has been a great support from your side.

    Regards,

    Pradeep