Tool/software: WEBENCH® Design Tools
Phase Noise Plot Not Modeling as Expected
If the LMK04832 part is programmed for jitter cleaning i would have expected the total output phase noise to better model the PLL phase noise plot rather than just slightly improving on the input reference mask. Can anyone offer up some advice?
See the image below:
Hello Austin,
When loading the LMK04832, you will have the option of selecting PLL1 or PLL2 for simulation.
Simulating dual loop devices in PLLatinum sim requires first simulating PLL1, saving the output, and using that as the input to PLL2. Now often you may not need to bother with the first step and you could just use the open loop VCXO phase noise profile as your reference for PLL2. However if you are concerned about phase noise around/below the loop bandwidth of PLL1 or are concerned about the attenuation PLL1 will provide a particularly noisy input, you should go ahead and simulate PLL1 first, save those results and use that as the input to PLL2.
Jitter cleaning is done in PLL1 with a narrow loop bandwidth and VCXO to provide PLL2 a clean and high frequency reference for frequency multiplication.
Please refer to the choosing loop bandwidths presentation in the files section of this E2E group. This is a direct link:
73,
Timothy
