hi,
I have a clock signal 125MHZ single ended LVCMOS 3.3V at the input, and I need to divide it by 5 to generate 25MHz LVCMOS 1.8V at the output.
We could make this inside an FPGA however we are afraid of jitter generation, so we think to make it externally.
Any advice?
Thansk a lot in advance
KR
Vincenzo