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LMX2594: RAMP0_NEXT trigger rising edge timing

Christer Andersson
Intellectual 290 points
Part Number: LMX2594
Other Parts Discussed in Thread: LMX2491

Hi,

We want to use Trigger A to trigger the next ramp ramp segment in automatic ramping mode. We intend to do this by assigning Trigger A to RAMP_CLK rising edge and letting our FPGA generate a pulse on that pin.

Imagine I want to generate a sawtooth FMCW waveform, e.g.

RAMP0_LEN = 50000 (up-ramp)

RAMP1_LEN = 1000 (down-ramp)

...

What are the timing requirements on RAMP_CLK rising edge in order to ensure we get exactly 50000 and 1000 CLK cycles per segment without jittering?

Thanks,

Christer

  • 0
    TI__Guru** 108550 points

    Hi Christer,

    in automatic ramping mode, you don't need Trigger A.

    You should make RAMPx_NEXT_TRIG = 0 = Timeout counter. Then once RAMP0 is completed, it will automatically go to RAMP1, and vice versa.

    Datasheet section 7.3.13.2.1 has an example.

  • 0 in reply to Noel Fung
    Intellectual 290 points

    Hi,

    Sorry, you misunderstood the question as it was a simple example (we understand how to use automatic ramping).

    We want to control the triggering of each ramp segment from our FPGA. In this way we can control the delay between ramps, e.g.

    • Trigger RAMP0 (50000 CLKs)
    • At completion of RAMP0 the FPGA waits a programmable/variable number of CLKs
    • Trigger RAMP1 (1000 CLKs)
    • At completion of RAMP1 the FPGA waits a programmable/variable number of CLKs
    • Repeat

    In the datasheet there isn't really anything about the timing requirements/constraints on using the triggers, e.g.:

    • Delay from trigger to ramp segment start
    • Position of RAMP_CLK rising edge relative CLK edge
    • How soon after RAMP0 completion one can trigger RAMP1 (hopefully immediately)
    • ... etc

    Thanks,

    Christer

  • 0 in reply to Christer Andersson
    TI__Guru** 108550 points

    Hi Christer,

    I am afraid your operation is not supported in LMX2594. This is because you don't know when is the ramp completed.

    LMX2491/92, a PLL only device, supports your operation. You can program the device in the way that once a ramp is completed, a flag is automatically raised (output a HIGH in an I/O pin) to acknowledge you the completion of the ramp. Your FPGA can start to count and issue a trigger signal to start the next ramp.