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LMK04828: External Sync Issue

SHENGXIANG ZHU88409
Prodigy 220 points
Part Number: LMK04828


Hello, everyone. I used a LMK04828 to generate SYSREFs for several ADS54J60s on my AD board. I used Clkin1 as Fin(External VCO mode) with a differential 500MHz clock. I left my CLKin0 and OSCin NOT connected.

Now I have no problems of alignment and latency issues of JESD204B because I have solved them in my FPGA design. But I have another board which gives a periodic signal and its clock to the FPGA of the AD board. My requirement is to synchronize the periodic signal with the SYSREFs.

I used the periodic signal and its clock to generate a One-shot pulse for the sync port of LMK04828. I configured it just like 9.3.2.1.1 and 9.3.3.1.1 of the datasheet. To allow SYNC to effect dividers: SYNC_DIS0 = 0, SYNC_DIS2 = 0, SYNC_DIS4 = 0, SYNC_DISSYSREF = 0, then SYSREF_MUX =1 to use normal sync mode, then perform sync by my own sync pulse, prevent SYNC (SYSREF) from affecting dividers: SYNC_DIS0 = 1, SYNC_DIS2 = 1, SYNC_DIS4 = 1,SYNC_DISSYSREF = 1 , then SYSREF_CLR = 0 , finally SYSREF_MUX = 3 because I chose continuous SYSREF mode. However, every time I power up the AD board (with another board not changed) or reconfigure the LMK04828, the phase difference between the SYSREF and my periodic signal is different ! It showed me that the LMK04828 was NOT synchronized.

I have some questions as follows.

1)      Is my requirement feasible ? What’s wrong with this ? How can I solve the problem?

2)      9.1.11 described two types of 0-delay mode. “Without using 0-delay mode there will be n possible fixed phase relationships from clock input to clock output depending on the clock output divide value.” However, they both use Clkin1 as FBCLKin mode but I use Clkin1 as Fin mode. Then I can do nothing to change it, right? Must I use 0-delay mode to meet the requirement ? Which registers need to be configured to implement 0-delay?

3)      SYNC_1SHOT_EN can be configured as level sensitive or edge sensitive. I used a one-shot sync pulse and I can NOT find any difference between them in my test. Could anyone explain it for me ?

4)      Some topics in the forum mentioned Re-clocked sync mode but the datasheet does not explain it in detail. Is it useful to meet my requirement? What’s the procedures to use Re-clocked sync mode ? Just enable it before the sync event ???

 

Please help me. Thanks.

  • 0
    TI__Genius 16845 points

    Thanks for posting on E2E. I have assigned your post to the responsible engineer. He will respond to you soon.

    Kind regards,
    Lane

  • 0
    TI__Mastermind 34270 points

    Greetings,

    Lane pointed me to this thread. Can you provide a register programming file (or a .tcs file, if using TICS Pro) showing the register programming state just before generating the SYNC pulse? To upload a .tcs file, please put it in a zip file first.

    1. I believe your requirement should be feasible. If I can get the register programming state, I can help to look into why the SYNC may not be observed. Otherwise, it will take more time to duplicate the issue and find a valid programming sequence.
    2. 0-delay should not be required for this application unless you need to establish a deterministic relationship between the phase of PLL1 input clock (nested) or PLL2 OSCin clock (cascaded). If the outputs must establish a deterministic phase relationship to the external 500 MHz differential clock on the CLKin1 pins, 0-delay can be used.
    3. When using level-sensitive mode (SYNC_1SHOT_EN=1), as long as the SYNC pin is asserted, the outputs will be held in the SYNC state. When using edge-sensitive mode (SYNC_1SHOT_EN=0), the outputs will be SYNCed on the rising edge of the SYNC pin, and will only be held in the SYNC state for the minimum amount of time required to synchronize the dividers. This distinction is useful if the downstream clock devices are not able to accept clocks until some time after the LMK04828 edge-sensitive sync is complete.
    4. Re-clocked SYNC is more helpful for devices with training frames such as LM97600, which are non-JESD devices. I do not think it is useful for this application.

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 220 points

    Hi , Lane and Derek, thank you  for your quick answer.

    The register file (uploaded as config_1.zip) is written by my colleague without using TICS Pro.

    I would explain it according to my understanding.

    The 800000 is used just as a NOP operation because it only read the register.

    According the programming sequence of the file,

    after the 014400 is configured,

    I generate a sync_ready signal to inform my FPGA logic to give the one-shot sync pulse .

    After the sync pulse is asserted then deasserted, my FPGA logic  would generate a sync_finish signal to

    inform the SPI configuration module to resume configuring the subsequent registers  0144FF to 1FFFFF.

    Please help me to find out what's wrong with the file.

    Thanks.

    config_1.zip

  • 0 in reply to SHENGXIANG ZHU88409
    Prodigy 220 points

    Sorry for late reply. I solved the problem by myself two weeks ago.

    I used the TICS pro software at first, but it is so complex in the configuration of "CLKin and PLLs".

    It always reported some errors such as " Set CLKin_OUT_MUX to drive PLL1" or a invalid VCXO frequency with red color fonts.

    Then I used the software of ADS54JXX which has also the function of configuring LMK04828.

    It is relatively easy to use.

    I reconfigued the registers from 000 to 17D.

    Then I configured some registers again like  the example of the datasheet,

    which I used my external sync instead of the SPI sync.

    It worked finally !!!

    Anyway, thanks again !!!

    IMG_tics.zip