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LMX2595: Close by sour

Part Number: LMX2595
Other Parts Discussed in Thread: , USB2ANY

HI Ti,

We are working on LMX2595 PLL and we are generating 0.5GHz to 18 GHz frequency in steps of 1MHz.

We have mounted the LMX2595 in our card with FPGA in it. For changing frequency we are programming only 7 registers + R0 register which are mentioned below.

R75 CHDIV
R46 OUTB_MUX,Channel divider,VCO,SysRef
R45 OUTA_MUX,Channel divider,VCO,VCO2X
R43 PLL_NUM[15:0]
R37 PFD_DLY_SEL
R36 PLL_N
R27 VCO2X_EN


With this register we are getting lock at all frequencies without any issues. 

But the issue is close by spurious. When I programm the LMX2595 using our FPGA we are getting more close by spurs at 125Khz, 250Khz and 500KHz away.( My test frequencies are 15001,15201,15199 MHz etc) spur level is -40dbc. I am using 50KHz Loop bandwidth

But when I programm the LMX2595 mounted on our card using Ticpro software( Here I am by passing the on board FPGA and I am taking the SPI from LMX2595EVM), I am not getting any spurs( spur level is -55dbc).

I checked the registers value of both methods, they are the same(charge pump current is also same). But only spurs are high when I programm through on board FPGA.

My doubt is, other than those 7 register and R0 registers, do we need write any other register. So that spurs will get reduced.

On board FPGA register map	Tics pro register map	
0x700000			0x700000	R112
0x6F0000			0x6F0000	R111
0x6E0000			0x6E0000	R110
0x6D0000			0x6D0000	R109
0x6C0000			0x6C0000	R108
0x6B0000			0x6B0000	R107
0x6A0000			0x6A0000	R106
0x690021			0x690021	R105
0x680000			0x680000	R104
0x670000			0x670000	R103
0x660000			0x660000	R102
0x650011			0x650011	R101
0x640000			0x640000	R100
0x630000			0x630000	R99
0x620000			0x620000	R98
0x610888			0x610888	R97
0x600000			0x600000	R96
0x5F0000			0x5F0000	R95
0x5E0000			0x5E0000	R94
0x5D0000			0x5D0000	R93
0x5C0000			0x5C0000	R92
0x5B0000			0x5B0000	R91
0x5A0000			0x5A0000	R90
0x590000			0x590000	R89
0x580000			0x580000	R88
0x570000			0x570000	R87
0x560000			0x560000	R86
0x550000			0x550000	R85
0x540000			0x540000	R84
0x530000			0x530000	R83
0x520000			0x520000	R82
0x510000			0x510000	R81
0x500000			0x500000	R80
0x4F0000			0x4F0000	R79
0x4E0003			0x4E0003	R78
0x4D0000			0x4D0000	R77
0x4C000C			0x4C000C	R76
0x4B0940			0x4B0800	R75
0x4A0000			0x4A0000	R74
0x49003F			0x49003F	R73
0x480001			0x480001	R72
0x470081			0x470081	R71
0x46C350			0x46C350	R70
0x450000			0x450000	R69
0x4403E8			0x4403E8	R68
0x430000			0x430000	R67
0x4201F4			0x4201F4	R66
0x410000			0x410000	R65
0x401388			0x401388	R64
0x3F0000			0x3F0000	R63
0x3E0322			0x3E0322	R62
0x3D00A8			0x3D00A8	R61
0x3C0000			0x3C0000	R60
0x3B0001			0x3B0001	R59
0x3A8001			0x3A8001	R58
0x390020			0x390020	R57
0x380000			0x380000	R56
0x370000			0x370000	R55
0x360000			0x360000	R54
0x350000			0x350000	R53
0x340820			0x340820	R52
0x330080			0x330080	R51
0x320000			0x320000	R50
0x314180			0x314180	R49
0x300300			0x300300	R48
0x2F0300			0x2F0300	R47
0x2E07FC			0x2E07FD	R46
0x2DC0DF			0x2DD0DF	R45
0x2C1FA3			0x2C1FA3	R44
0x2B0000			0x2B0000	R43
0x2A0000			0x2A0000	R42
0x290000			0x290000	R41
0x280000			0x280000	R40
0x27C350			0x27C350	R39
0x260000			0x260000	R38
0x250304			0x250304	R37
0x240028			0x24002D	R36
0x230004			0x230004	R35
0x220000			0x220000	R34
0x211E21			0x211E21	R33
0x200393			0x200393	R32
0x1F43EC			0x1F43EC	R31
0x1E318C			0x1E318C	R30
0x1D318C			0x1D318C	R29
0x1C0488			0x1C0488	R28
0x1B0002			0x1B0003	R27
0x1A0DB0			0x1A0DB0	R26
0x190C2B			0x190C2B	R25
0x18071A			0x18071A	R24
0x17007C			0x17007C	R23
0x160001			0x160001	R22
0x150401			0x150401	R21
0x14E048			0x14E048	R20
0x1327B7			0x1327B7	R19
0x120064			0x120064	R18
0x11012C			0x11012C	R17
0x100080			0x100080	R16
0x0F064F			0x0F064F	R15
0x0E1E10			0x0E1E10	R14
0x0D4000			0x0D4000	R13
0x0C5001			0x0C5001	R12
0x0B0018			0x0B0018	R11
0x0A10D8			0x0A10D8	R10
0x091604			0x091604	R9
0x082000			0x082000	R8
0x0740B2			0x0740B2	R7
0x06C802			0x06C802	R6
0x0500C8			0x0500C8	R5
0x040A43			0x040A43	R4
0x030642			0x030642	R3
0x020500			0x020500	R2
0x010808			0x010808	R1
0x00251C	0x00251C	R0

  • Hello Pradeep,

    Aside from the registers described above, the only difference in the register files I could see was the output power on one of the channels, which I do not think is responsible for the observed difference in spur levels. In theory, there should be no difference writing SPI from an FPGA or from a USB2ANY.

    The case in register.txt has R43 = 0, so I cannot see what fractions are being written. Is it possible that TICS Pro is altering the fraction for these cases? Do the spurs return with TICS Pro when "Simplify Fraction" is pressed?

    Does the FPGA communicate to other devices on the SPI bus while the output spurs are being measured? It could be that SPI noise is mixing into the output.

    Are there other systems running on the FPGA card, which are powered down or unclocked while operating the SPI bus with the USB2ANY?

    Regards,

  • HI Payne,

    Thanks for the immediate response.

    Please find the answers inline.

    The case in register.txt has R43 = 0, so I cannot see what fractions are being written. Is it possible that TICS Pro is altering the fraction for these cases? Do the spurs return with TICS Pro when "Simplify Fraction" is pressed?

    We are keeping F den to 50000 and changing F num as required. Simplifying fraction is not reducing spur power level. R43 changes for different frequencies

    Does the FPGA communicate to other devices on the SPI bus while the output spurs are being measured? It could be that SPI noise is mixing into the output.

    NO,  PLL is the only SPI device on our card. Once SPI is return I am not seeing any noise on the SPI lines. So there must be problem with SPI line noise.

    Are there other systems running on the FPGA card, which are powered down or unlocked while operating the SPI bus with the USB2ANY?

    This is Artix 7 FPGA and it is connect to only our card with RF switches and PLL. There is nothing else.

    Even when I taken out FPGA SPI line and connect to LMX2595EVM card, I am facing the same issue. Spurs are more.

    We think it has to be some issue with register writing not with the hardware. 

     

  • Pradeep,

    Okay, I understand now. These spurs are likely fractional spurs or integer boundary spurs. There are a few mitigation strategies:

    • Adjust the phase detector frequency away from a multiple of the VCO frequency. There are two dividers and a multiplier in the input path to help shift the reference frequency to more favorable locations.
    • Adjust the modulator order if possible. This may not necessarily remove the spurs, but it could help shift them away from undesirable locations.
    • Increase the fractional denominator and allow slight frequency error with a denominator slightly offset from the exact value. This is not always allowable, but can be very practical if exact frequency is not required. The larger fraction can help spread out the fractional spur energy across a wider overall range.
    • Adjust the MASH_SEED registers (R40 and R41) to change the phase offset to something more favorable. This may not always work, but it is a helpful trick. Even setting MASH_SEED = 1 can sometimes help a lot.

    Regards,