LMX2492EVM: Relationship between ramping frequency step size and PLL bandwidth

Hello Darryn,

It may be helpful to think of this problem as a sequence of transient responses to the frequency change. Depending on the loop bandwidth, the phase margin, and the gamma, a transition from frequency F1 to frequency F2 can have some overshoot and undershoot which impacts linearity. It is not a function of loop bandwidth alone. Take a look at the transient response section of Dean Banerjee's PLL book for more information.

You want to optimize the loop parameters such that (F2 - F1) / rise time <= ramp rate. The update rate of the LMX2492 N divider in ramp mode is governed by the phase detector frequency, so the time spent at any one frequency is not very long - which causes any frequency error seen in the ramp to be well outside of the loop bandwidth, even for large loop bandwidths. As you said, the loop filter smooths the transition. And realistically, the fractional spurs should not have much impact, again because the time spent at any one frequency is not very long. 

Your step size will ultimately be constrained on both sides: the largest step size is constrained by your ramp rate requirements, which will set a minimum loop filter bandwidth needed to achieve the desired ramp rate; then the loop filter bandwidth will help set an appropriate minimum for the phase detector frequency, which constrains minimum step size (since a new ramp is initiated each phase detector cycle). I would also pick a step size smaller than the loop bandwidth to avoid cycle slipping issues.

TI's PLLatinum Sim is a fantastic tool for speeding up the computation of loop bandwidth, lock time, etc. 

Regards,