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LMK04610: Need assistance in configuration

Ed Gouweloos
Intellectual 260 points
Part Number: LMK04610

Please can someone provide assistance in configuration of PLL2 for the LMK04610.

Input clock is (CLK1) 50MHz. So I would guess to have PLL2 VCO at 6GHz, DIV6 so output of PLL2 will be 1GHz.

But then, what are the correct settings for the PLL2 in this case?

Thanks in advance!

EG

  • 0
    TI__Mastermind 33680 points

    Hello Ed,

    TICS Pro software includes a PLL2 loop filter calculation tool that helps determine the appropriate settings for PLL2_PROP, PLL2_INTG, and the integrated loop filter components based on the desired loop bandwidth. As for the phase detector, I would set the input to doubler inverting mode to increase the phase detector frequency as much as possible, since generally a higher phase detector frequency corresponds to lower output phase noise.

    Are you using PLL1 to cascade into PLL2? If not, set PLL1EN=0, the PLL2_EN_BYPASS_BUF bit must be set to 1, and PLL2_GLOBAL_BYP must be set to 1 to select CLKin1. After that, CLKIN1_EN should be set, the R divider can be set to 1, and CLKin1 may be forced to choose CLKin1 by setting CLKINSEL1_MODE=2, SW_REFINSEL=2, and CLKINBLK_ALL_EN=0. Otherwise, I can provide some guidance on setting PLL1 if needed.

    Regards,

  • 0 in reply to Derek Payne
    Intellectual 260 points

    Hi Derek,

    TICS Pro is what we are using right now. I have read a post a colleague of yours regarding the use of PLL1 and since we do not have an extremely critical application we most likely can leave PLL1 out.

    We were trying to start with the buttons in "Operating Mode" and then work our way through the rest of the settings. However, the tool PLL2 Loop Filter is stil a bit foggy to me.

    It calculates:

    CP-I and CP-P, PLL2_DIV, PRE_SCALER, CFILT, RFILT, CPROP but if I get to the PLL2 page
    then I also see PLL2_CSAMPLE, PLL2_INTEGRAL_INIT_VALUE. What should these be?

    Thank you very much in advance.

    Ed

  • 0 in reply to Ed Gouweloos
    TI__Mastermind 33680 points

    Hi Ed,

    Unless you are very concerned about achieving the absolute minimum lock time for PLL2, the settings of PLL2_INTEGRAL_INIT_VALUE and PLL2_CSAMPLE will not make much difference. Leaving them at the default values should be fine.

    Regards,

  • 0 in reply to Derek Payne
    Intellectual 260 points

    Hi Derek,

    Thanks again. Just to make sure that we had everything right.
    Currently I think we have a hardware problem, it seems that internal the LMK is oscillating at some strange frequency not related to the VCO.
    So we see ~ 40MHz output, almost regardless of divider settings .... looking at the hardware I see that the capacitors that should be 10uF are 1uF instead! (PLL1_CAP, PLL2_VCO_LDO_CAP and PLL2_LDO_CAP). This is something we have to fix before continueing with testing.

    Anyway, that is a different issue. By the way, I missed the spec on when the device is ready after releasing the RESETn, is that really 0?

    Kind Regards,
    Ed

  • 0 in reply to Ed Gouweloos
    TI__Mastermind 33680 points

    Hi Ed,

    Quick confirmation: you are starting the device after programming the registers, right? (0x11 = 0x01)

    There is a POR clock that runs the internal state machine before lock is established, and that may be feeding through. But it seems strange to me that this output would ever feed through in the first place. On the PLL2 page, are the PLL2_BOTTOM and PLL2_TOP buffers enabled, and set to the CLKout path (elsewhere called VCOPRESCPLL2_freq, the output of the VCO prescaler)?

    As I said elsewhere, SPI is ready as soon as RESETn=1. The reset throws away the old register configuration and asynchronously reloads the preset values, so the timescale for that operation is tens or maybe low hundreds of nanoseconds. Even if you started a SPI transaction the instant the reset cleared, it would still take around 800ns to generate and decode an address for SPI reading; SPI writing will take longer. So there should be no issues performing SPI transactions immediately after exiting reset.

    Reset also resets the internal state machines, which should prevent the register contents from affecting the device until the device start signal is sent. I don't know if you can send the device start signal immediately after RESETn=1. Usually the process of programming all of the SPI registers is long enough that this isn't an issue.

    Regards,

  • 0 in reply to Derek Payne
    Intellectual 260 points

    Hi Derek,

    Thanks for the answer. Yes, with the device-start button on the TICSPro tool 0x11 is written with 0x01 and then with 0x00.

    However, even with your suggestions I am not able to create an output clock based on PLL2.

    As said, I can based on the BYPASS examples.

    Would you be able to provide me with a sure-to-work config for PLL2?

    So XO 50MHz is on CLKIN1 (we leave the VCXO of 50MHz out of the equation right now) and let's say we just wanted 100MHz on all outputs/

    What would be the sure-to-work config file in TICSPro ?

    Thanks again,

    Ed