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LMK04610: Selecting correct loop bandwidths for PLL1 and PLL2

Jeff Philips28
Prodigy 140 points
Part Number: LMK04610

Dear TI,

I'm successfully using TICS Pro to communicate with the LMK04610s on both your evaluation board and my board.  I think you can ignore my previous posts, and I think I closed them.

I'm using the LMK04610 as both a jitter cleaner and clock generator.  I'm using a 100MHz TCXO and a 100MHz VCXO.  I'd like to achieve 75-100fs rms jitter on a 200MHz clock over an 80MHz bandwidth.  The only remaining issue is correctly setting the PLL1 and PLL2 loop bandwidths.  I have phase noise versus offset frequency for the TCXO I'm using as a reference for PLL1, but I don't have a figure of merit for PLL1 to determine the height of its noise pedestal.  Similarly, I need phase noise versus offset frequency for the VCO used in PLL2 as well as a figure of merit for PLL2.  I think with all that information (that doesn't appear to be in the data sheet) I can select the PLL1 and PLL2 bandwidth's appropriately.  I have read Timothy Toroni's paper on choosing loop bandwidths for PLLs.

Am I on the right track, or is there adequate information in the data sheet to choose loop bandwidths?

If you reply to this request, your reward will be me leaving you in peace and tranquility.

Thank you, Jeff

  • 0
    TI__Mastermind 28560 points

    Hello Jeff,

    I'm not sure the PLL1 FOM will be critical... You mention wanting 75 to 100 fs rms on a 200 MHz clock over an 80 MHz bandwidth.  What is the starting integration range?  12 kHz, 100 Hz,  Other?

    I presume you also have the phase noise info for the VCXO?  This is even more important than the TCXO.

    Generally for jitter cleaning functionality, PLL1 phase noise spec isn't critical as you are not trying to optimize the loop bandwidth, just set it narrow.  For example using PLL1 tool set 20 Hz as desired loop bandwidth, then calculate and apply the filter.  Note the VCXO noise is also very important in addition to the TCXO.

     * Out of curiosity, at what offset does the TCXO and VCXO noise cross (when phase noise is normalized to same frequency)?

    Do you have any phase noise measurement equipment to test with as you optimize?  Or perhaps you are using an ADC which you can measure performance with a clean analog input?

    I have found that with a clean reference to PLL2, maximizing PLL2_PROP value to 63 would result in best phase noise performance.  I used a PLL2_INTG = 4 in this case.

    73,
    Timothy