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LMK04828: PLLatinum Sim component blank issue

Part Number: LMK04828

I am using PLLatinum Sim version 1.5.4.0 and can not get the 4th order filter for VCO0 or 1 to work? 

I can not "Blank out" the component values in the Force Component Values section on the filter design tab?  So when I re-calculate the filter design the phase noise plots don't look correct and I cant seem to get to the original value as when I "loaded" the component.  I don't know if I can trust the results the tool is showing me? 

In a 3rd order filter design, does "integrated Component" mean its a Forced component?

  • Hi Tony,

    Generally, if PLLatinum Sim calculates a value without indicating "design failure" then it can be considered a valid calculation. Forced components are usually reserved for cases where the device includes integrated loop filter components. The LMK04828 is a 4th order device with integrated 3rd and 4th order components, so it doesn't make sense to calculate results for VCO0/1 with anything less than 4th order. To modify the 1st and 2nd order components, use the Loop Filter Components box in the upper left panel, and do not use the forced component values. To modify the 3rd and 4th order components, use the Forced Component Values and recalculate the loop filter. You can technically use the Loop Filter Components box, and it should update immediately; but if you respecify design targets in Filter Parameters and click Calculate Loop Filter, it will overwrite the loop filter with the Forced Component Values.

    As for "blanking out" forced component values... it seems that null user inputs are "corrected" to 0, despite null input being initially valid and being handled differently than 0. I'll make sure that the next version handles the Forced Component Values (and their interaction with integrated components in the Loop Filter Components box) a little more intelligently.

    For now, a workaround in case you "soft-lock" PLLatinum Sim by tweaking a "forbidden" forced component value: go to Select Device, select a different device, then reselect the original device and reload; this should reinitialize the forced component values, including the nulls.

    Regards,

  • Derek

    If the device is using "integrated" components, do I need to program these values?  If so how?

    Also, if R3 and R4 are calculated as "0", this looks like for the parameters I picked, the SW is calculating a 2nd order filter?  Is this correct?

    Parameters: Fosc=125 MHZ, Fpd=62.5, Kpd=3.2 ma, Fvco=3062.5, VCO1 selected, N=49 and Fout=437.5 MHz

    Tony

  • Tony,

    The device does have integrated components which should be programmed - see registers 16C and 16D. In PLLatinum Sim, the programmable values are already pre-loaded into the Forced Component Values for C3, C4, R3, and R4.

    The loop filter merges C1 with C3 when R3 = 0, and C1 with both C3 and C4 when R3 = 0 and R4 = 0. This effectively renders the loop filter second order. However, 0Ω is not a valid value for the loop filter on PLL2 of LMK04828, which is why I said earlier that all calculations should be 4th order.

    The integration of the LMK products into PLLatinum Sim is a recent development; most prior products were LMX devices with more flexible loop filter order, so it made sense to allow simulation of every filter order. To prevent confusion about loop filter design for LMK devices, our next update should remove invalid filter orders for parts with integrated components, and deactivate user input on integrated components in the Loop Filter Components box.

    Regards,

  • OK, here's what I have found. 

    It looks like the PLLatinum Sim SW does not set R3 and R4 correctly when optimizing for jitter.  If, from a fresh load of the part, set the PLL2 for the values I stated in my last post, The values in the Loop filter components has C3 = C4 =0, and has R3=R4 = 0.2k.  In the Forced component window, C3=C4=0.01nf and every other value is blank.  If I then hit the "Calculate Loop Filter", The "Design Warnings" state 1) The components not a Number - Reverting to Original Value, 2) Design Failure, and 3) Design not supported?  The Phase Noise Plot looks reasonable, and the loop BW was calculated as 154.3 KHz, with jitter 115.5 fs with optimizer turned off.  If I then turn on the optimizer and set Jitter, The Phase noise plot starts at -40 dBc @ 1e2 and I get the same Design Warnings?

    If I then "Force Component Values" for R3=R4=0.2k (the lowest programmable value), when I re-calculate the loop filter, I get reasonable results, Phase noise at -112 * 1e2 and Jitter= 118.6 fs, with a loop BW = 261.87 KHz. I think this is a good result, the Design Warnings - Fixed Components restrict BW.  Can I trust this Result?  If I keep hitting the Calculate loop filter, it calculates different loop band widths and sometimes the warning does not show up?  Loop BW changes as it tries to optimize for jitter, this seems normal for a Monte Carlo type of optimizing.  Is this what its doing?

     

  • Tony,

    If I load the device and so as you say, I get the same warnings.  So if C3_Fixed and C4_Fixed are there, but R3 and R4 are not, then there is an issue.

    Maybe in the next release, we can try to address this.

    The forced components restricting loop bandwidth warning comes up and some ways to deal with this are (1) increase charge pump gain, (2) increase phase detector frequency, (3) reduce integrated component values, (4) reduce phase margin, (5) increase gamma optimization parameter.

    The optimizer uses the Hook-Jeeves method and you are seeing something converge very close.  You can sometimes see small difference if you press the button repeatably.   In this situation, a wider loop bandwidth is needed, but it is being restricted by the forced components.  So the optimal solution is just at the point where the loop bandwidth is restricted by the forced components.  So it makes sense why sometimes you see the warning and sometimes not.

    Regards,

    Dean