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LMK04616: low skew mode

Part Number: LMK04616
Other Parts Discussed in Thread: LMK04832

Hi

What is the CLKinX to CLKOUTX propagation delay (min and max) (without PLL1) ( part to part variation )?

How much the propagation delay changes over temperature? 

In "Low Skew Mode"  ,what is the skew in psec? (min and max)?

In "Low Skew Mode"  , what is the variation of Low skew and propagation relative to the temperature?

SYSREF

Does the sysref align with the clkinX?

  • Hello Shlomi,

    Note, we are currently releasing an updated data sheet, in it we are using the term zero delay mode (ZDM) throughout the datasheet instead of low skew mode to match terminology with our other devices.  Note that through timing delays, the non-feedback clocks can be adjusted to have nominally 0 delay with input within the range of delay adjustment as with other devices such as LMK0482x or LMK04832.

    Prop delay changes from about 6.9 ns at cold to 7.6 ns at hot when using PLL2 with CH6 feedback divider.

    --

    As for SYSREF, it depends if SYREF is used for the feeback.  My understanding is if CH6 is operating as SYSREF, then rising edge of SYSREF would be 7.3 ns delayed from input.  Of course using lower frequencies for feedback will reduce the maximum possible phase detector frequency.  Also, if you have a 100 MHz reference and a 10 MHz SYSREF, then providing a 100 MHz clock for feedback would allow alignment of SYSREF to input as is an edge of 100 MHz reference for every 10 MHz edge.

    73,
    Timothy

  •  Hi

    you are writing about CLKOUT6??  Did you mean CLKOUT7??

     

    I have attached the connection block.

    I need the information about:

    1. the prop delay between CLKinX to CLKOUT7 and variation over Temp? (in zero delay).

    2. At the second LMK the prop delay between OSCin to each of the CLKout and variation over Temp? (in zero delay).

     

    Thank,

    Shlomi

  • Hello Shlomi,

    The updated datasheet is now available.  In it you will find the update note about CLKout7 to CLKout6.  Note that CLKout6 and 7 share a divider.  But if you were to turn on analog delay for only CLKout6, you would find that to cause the phase adjust, not CLKout7.

    The prop delay to other CLKouts would be covered by the skew specification.

    73,
    Timothy

  • Hi

    I need to phase align 2 separate system.

    as in the block diagram attached:

    I need all 32 channels to be phase align.

    the RF ferq - 1.5GHz

    the is 1 CLK REF 10MHz top both system.

    The alignment need to be over Temp -5C to 60C.

    That why I asked about the delays.

    Do you have any suggestions?

     

    thanks

    Shlomi

  • Hi Shlomi,

    If you need the edges of the clocks to all fall as closely as possible to each other, matching the line lengths and configuring the LMK04616s in zero-delay mode will bound the phase misalignment to within the variation in propagation delay. In theory, if the supply voltages are kept constant and the temperatures of the LMK devices are similar, the variation from these sources should be minimized between parts. However, there will still be some part to part and channel to channel variation, which cannot be avoided without a secondary control mechanism implemented by the user (binning, per-output calibration, etc).

    Best of luck,

  • Hi Derek

    I can't understand the phase relationship between the ClkinX and the sysclk.

    Can you please see the attached wave-forms:

    Assume the asynchronous sync pulse inserted to the clock distributed at SYNC 1 time or SYNC 2.

    My question:  Where will the sysclk appear in this timing diagram in case of pulse at SYNC 1 and in case of SYNC 2?

    Will it appear in the same place (time) in both cases?

    Thanks

    Moti

  • Derek\ Hi

    I am waiting for your answer to Moti question

    Shlomi

  • Moved to new thread:

    73,
    Timothy