LMK04828: PLL 1 and PLL 2 will not lock.

Just for clarification. The link is not the Loop filter values. The link got misplaced while I was uploading the hex values. Not sure how it got placed in the middle of the page. Anyway, the link has all of the register hex values. 

Thanks for looking.  

Hi Scott,

Thanks for providing the hex values, it makes it very easy to see how the PLL was configured. I see two things that are likely causing problems:

1. I entered the values you specified into PLLatinum Sim, and I calculate that your loop bandwidth is around 10 Hz. Given that the phase detector frequency is almost six orders of magnitude faster, I suspect PLL1 is cycle slipping. A quick way to check this is to set the STATUS_LDx pins to display the PLL1 N/2 and PLL1 R/2 output values, and probe them on an oscilloscope. You can also configure PLL2 as an OSCout buffer, and use this to monitor the behavior of the VCXO with a frequency counter or a phase noise analyzer transient measurement. If you do see cycle slipping causing problems, the quickest resolution is to increase the loop bandwidth.
2. You are operating OSCin very close to the datasheet maximum frequency rating. Technically, if there is any positive frequency offset on the 10 MHz input, the OSCin spec is being violated. Operating this close to the OSCin maximum frequency rating is not recommended, and I strongly suggest picking a lower frequency VCXO if possible. And for performance reasons, a 500 MHz VCXO may not be optimal anyway: the close-in noise of a VCXO tends to degrade with increasing frequency. So it is often a better idea to use the lowest VCXO frequency needed to achieve a reasonable PLL2 phase detector frequency (e.g. 100 MHz or 50 MHz with doubler enabled).

If neither cycle slipping or the OSCin frequency range are the source of the problem, we can continue debugging.

Regards,

Hi Derek,

Thank you for your reply. We unfortunately don't have access to the STATUS_LDx pins. We have been reading the registers 0x182 and 0x183 to confirm lock on PLL 1 and PLL 2.

At this point we have shifted our focus off of PLL1 and on to PLL2. We removed the 500MHz clock off of our board and attached a function generator to supply our clock into OSCin*. This is single ended. We adjusted our values in TICS Pro for a 100MHz clock, keeping the same values for the loop filters. At this point when querying registers 0x182 and 0x183, we now see that we have the lost lock bit engaged. Meaning that we had lock but lost it. This is an improvement, but we need lock. 

I Uploaded a picture of a portion schematic which shows the loop filters and the oscillator. Like I said earlier, we did remove the VCSO on one of our boards and attached a function generator to allow for different frequencies. 

Hi Scott,

https://e2e.ti.com/support/clock-and-timing/f/48/p/829826/3070798#3070798 In this post it sounds like you are preparing to do another board revision. Is there any further debugging you would like to attempt with this revision?

Regards,