Problems with one of three DAC cards / Redirected by Kang Hsia TI

Hello Valentin,

As suggested by our colleague, the VCO ranges are ATE-tested. 158.5 MHz is close to the minimum achievable frequency for VCO0 divided by 15, so it may be possible that the VCO tuning voltage is clamping to one of the rails, or there is a poor soldering connection on a relevant pin. Try probing CPout2 pin, the local loop filter components, and the Vcc9_CP2 pin, and make sure the voltages fall within expected ranges. Vcc9_CP2 should be 3.3V; the tuning voltage and loop filter components should stabilize at a nonzero voltage at least a few hundred millivolts away from the supply and ground voltages.

The VCXO output may also be corrupted or the VCXO damaged, such that a large spur appears on the output and pulls the frequency. An oscilloscope FFT or a spectrum analyzer should be able to show any unusual spurs on the VCXO output. This explanation seems less likely to me, because PLL1 is locking. But PLL1 also typically has a much lower loop bandwidth, so it could be less susceptible to VCXO spurs above the loop bandwidth.

There are a few other things that could be responsible, like holdover mode failing to exit, an erroneous VCO calibration value (especially in 0-delay mode), or the charge pump polarity somehow becoming inverted. It seems unlikely that these failure mechanisms would be responsible, since the board firmware or the register defaults should be the same between different boards. But we can explore those options once the other more likely causes are ruled out.

Regards,

Hello,

We have not heard any response from you for over a week, so we can only assume that you have resolved your issue. I will mark this thread as resolved for now. If you do need further assistance please comment on the thread and we can continue to provide help.

Regards,

Hello,

Thanks for your reply. For the moment this is not helping.

Kind regards

Magdalena

Hello Magdalena,

Can you share the programming you have for the LMK04828?

As stated, the frequency ranges for this device are:

• VCO0 = 2370 to 2630 MHz
• VCO1 = 2920 to 3080 MHz

I'm not sure I fully understand.... but, "The adjustable frequencies are just within the range or next to it. Therefore, the output frequency can not be set exactly to 160 MHz (divided) but only to about 158.5 MHz. The two tested settings were:"

• Set VCO0 to 2400 MHz and Divider to 15 to divide to 160 MHz.
• Set VCO1 to 3040 MHz and Divider to 19 to divide to 160 MHz.

I think what you are saying is that your setup results in a phase detector frequency at PLL2 of 160 MHz.  If I understand correctly, if you are using 160 MHz for the phase detector frequency of PLL2, you are operating beyond the maximum 155 MHz specification.

• Or do I misunderstand and you are discussing the output divider from VCO to output?

If you do provide a 158.5 MHz reference for your *15 case, then the PLL2 VCO frequency would have to operate at 158.5 * 15 = 2377.5 MHz.  This is within the VCO0 range and I expect it to work.

If you do provide a 158.5 MHz reference for your *19 case, then the PLL2 VCO frequency would have to operate at 158.5 * 19 = 3011.5 MHz.  This is within the VCO1 range and I expect it to work.

Could you please check the register.  To ensure VCO calibration occurs properly, please ensure that OSCin_FREQ register is programmed correctly.  Register 0x162[4:2] should be programmed to...

• 2 if the OSCin frequency is 127 to 255 MHz
• 4 if the OSCin frequency is 255 to 500 MHz.

73,
Timothy

Hello,

Can you provided programming used and clarify any of the questions above, especially about OSCin_FREQ register?

What is the phase detector of the device operating at?

73,
Timothy