• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 22 subscribers
  • Views 575 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04821: Setting Required

krithika r
Prodigy 100 points
Part Number: LMK04821
Other Parts Discussed in Thread: LMK04832

Hi,

We are planning to use LMK04821 to clock the 12 ADC's. The clock output required from LMK04821 is 10MHz.

Can you suggest the settings required to generate 10MHz output, like clock input required and the register settings for LMK4821.

Please let me know at the earliest.

  • 0
    TI__Mastermind 33730 points

    Hello Krithika,

    The clock divider maximum is 32, the VCO post-divider for VCO1 is maximum 8, and the minimum frequency of VCO1 is 2920 MHz. 2920/(32*8) = 11.40625 MHz minimum output frequency. So PLL2 cannot be used to generate 10 MHz. Please consider using the LMK04832 instead, which has a maximum clock divide of 1023. 

    I have attached a .tcs file which can be used with TICS Pro software. In TICS Pro, use the menu for Select Device -> Clock Generator/Jitter Cleaner (Dual Loop) -> LMK04832, open the .tcs file using File -> Load, and review the settings on the pages "PLL1 and 2" and "Clock Outputs" for a basic suggestion.

    LMK04832_10MHz.tcs

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 10 points

    Hi,

    Thanks for the reply.

    Can I use only PLL2 and OSCin to generate the outputs, since I need to generate either of the three frequencies 10/25.6/40MHz based on the user selection at all outputs of LMK.

    Is that possible if i give VCXo for OSCin inputs and genrate these outputs.

    Please let me know at the earliest.

  • 0 in reply to krithika r1
    TI__Mastermind 33730 points

    Krithika,

    As I said before, there is no way to generate 10 MHz on all outputs using PLL2 of LMK04821.  

    The least common multiple of 10/25.6/40 MHz is 640 MHz. No multiple of 640 MHz can be generated using either VCO (including VCO1 with post divider).

    Once again, I recommend using LMK04832. I updated the settings file to show how, with a VCO frequency of 3200 MHz, LMK04832 can generate 10 MHz (chdiv=320), 25.6 MHz (chdiv=125), and 40 MHz (chdiv=80). 3200 MHz can also divide down easily to common VCXO input values such as 100 MHz. And 100 MHz divides evenly into many input values, such as the very common 10 MHz.

    LMK04832 10 25.6 40.tcs

    Regards,