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LMK04806: Questions about Register Settings & Clock Outputs

user6092165
Prodigy 70 points
Part Number: LMK04806


Hello,

We're now using Micro-Control Unit ( STM32 series ) to control LMK04806 chips and I have some questions:

1. We've tried the following steps to generate clock outputs:

(1) Control the DATAuWire,CLKuWire and LEuWire as shown in "Serial MICROWIRE Timing Diagram" and "Three Extra Clocks or Double Program" in the datasheet.

(2) We chose the Mode as "Single PLL".

(3) We would like to generate 2 200MHz, 2 80MHz,1 20MHz and 1 40MHz clock outputs with OSCin frequency of 80MHz ,according to chapter 9.1.4 "Frequency Planning with the LMK0480x Family", the calculated VCO frequency should be 2400MHz and the output dividers should be 12,30,120 and 60 respectively.

(4) Then we calculated the PLL2-relative parameters according to chapter 9.1.5.1 "Example PLL2 N Divider Programming",the results are:PLL2_R = 2 (with EN_PLL2_REF_2X = 1,OSCin frequency equals to PLL2 phase detector frequency) ;Total PLL2_N = 30 ( VCO frequency / OSCin frequency); PLL2_P = 2; PLL2_N = PLL2_N_CAL= 30 / 2 = 15.

(5) Finally,we programmed Register 0 - Register 31 as recommended in chapter 8.5.2 "Recommended Programming Sequence".

After completed the mentioned 5 steps,we could get outputs! Do I misuderstand any details? What should I do to achieve the correct result ?

2.To control LMK04806, do we need extra configurations(e.g.For I2C,we need to generate START and STOP signals) or just program the registers as the diagram shown in chapter 8.3 "Feature Description"(Timing Digram)?

3.In order to make sure the communication is correct,we tried to configure the LD pin's output as Low and High(which is described in chapter 8.6.3.5 R12) and we can get the correct output.

Looking forward to your reply,

Thanks & Best regards,

Xiaoting Zhang

  • 0
    TI__Mastermind 33830 points

    Hello Xiaoting,

    It sounds like you are following all the required steps to program the device. Can you make sure that the CLKoutX_Y_PD bits on each channel are set to 0, and that the clock output format is programmed to a value other than powerdown? Several of the clock outputs are powered down by default.

    Also, can you confirm that the output has the proper termination for your selected format? LVPECL and LVDS outputs require termination to function properly.

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 70 points

    Dear Derek,

    Thanks for your quick reply!

    1.Yes,all the CLKoutX_Y_PD bits are set to 0 and all the clock output formats are programmed to a value ( Either LVDs or LVCMOS ).

    2.Sorry,I don't understand the termination for selected format,can I find some details in the datasheet ?

    Best regards,

    Xiaoting Zhang

  • 0 in reply to Derek Payne
    Prodigy 70 points

    Dear Derek,

    I suddenly had an idea, is there any easy way to acheive a clock output? For example, can I use the default configurations by setting R0[17] "RESET"bits to 1 and then just open the CLKout_0_1_PD bits and set the clock output format as LVDs to get an output? Or something like that, just to get a quick output?

    I double checked the codes and asked my colleague about the termination thing( which is also meets the datasheet requirements),still don't get any idea to fix this problem. 

    Regards,

    Xiaoting Zhang

  • 0 in reply to user6092165
    TI__Mastermind 33830 points

    Hi Xiaoting,

    As long as the VCO is powered up, any output that is not powered down and which has an output format programmed will generate an output frequency. So the default configuration should already have at least one active output (CLKout6 or CLKout8). So you should be able to follow the reset procedure you described to get a quick output.

    Is it possible that the SYNC input has been asserted? Can you try toggling the SYNC_POL_INV bit, or setting NO_SYNC_CLKoutX_Y=1 on the appropriate channel, to confirm that the output dividers are not being held in reset?

    Is it possible that you have entered one of the external VCO modes? Double-check the programming on the MODE register.

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 70 points

    Hi Derek,

    I read the chapter 8.3.9.3 Clock Output Synchronization again and tried to set the NO_SYNC_CLKoutX_Y=1 and finally I can get outputs and they all meet my needs ! Thank you so much for your help!!

    But I still don't understand how can SYNC be used to hold the outputs in a low state? Although I get the result I want, I still want to know the reason about this.

    Thank you for your help again!

    Best regards,

    Xiaoting Zhang

  • 0 in reply to user6092165
    TI__Mastermind 33830 points

    Hi Xiaoting,

    I'm glad to hear you have outputs now!

    The SYNC feature is actually a divider reset. When the SYNC signal is asserted, the dividers are held at logic low because this is the default behavior during a reset. Normally, SYNC is used as a pulsed signal to reset the dividers at the same time, establishing a deterministic phase relationship between all the outputs. But it sounds like the SYNC input in your case was being continually asserted, so the dividers never exited the reset state. This could be because the SYNC_TYPE and SYNC_POL_INV register settings caused the SYNC signal to be asserted by default.

    Setting NO_SYNC_CLKoutX_Y=1 blocks the SYNC signal from holding the dividers in the reset state, so they can continue operating normally regardless of any SYNC input.

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 70 points

    Hi Derek,

    Thank you so much for your help!

    I think this issue can be closed:)

    Best regards,

    Xiaoting Zhang