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LMK04828: LVPECL IBIS simulation in Hyperlynx

Part Number: LMK04828
Other Parts Discussed in Thread: ADS54J40

Hello. 

I simulate LVPECL output LMK04828 for ADS54J40 in Hyperlynx, and get a bad result, when termination includes capacitors. Without them, the signal is normal.

termination with capacitors.

without capacitors

Also, I met different termination options:
with capacitors near LMK and near ADC, or only near LMK. 100 Ohm resistors before or after capacitors

I do not understand all the subtleties, and I would like to ask - which option is best for connecting to ads54j40. Can i use HSDS output?

  • Hello Eugene,

    The common-mode voltage for the LMK04828 LVPECL signal is 2.0V, whereas the ADS54J40 internally biases the pins to 1.15V through 400Ω. For LVPECL, I would recommend using capacitors near the ADS54J40, and termination after the capacitors. I think the same termination should be applicable to HSDS and LVDS, because the common mode voltages for these outputs are all still higher than the internal biasing supplied by the ADS54J40.

    We routinely use capacitors and 100Ω differential termination with our LVPECL outputs for characterization. I am not sure why our simulation results are showing such poor performance with capacitors. Consider asking this question to the team for the ADS54J40 as well, they may have more insights for you.

    Regards,