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LMK04832: Cannot get PLL2 DLD to work

Bart Handels
Prodigy 20 points
Part Number: LMK04832


Hi,

I am using a board with an LMK04832 device. On this board the LMK get 2 clock inputs. CLKin0 is connected to a 10MHz TCXO, OSCin is connected to a 122.88MHz VCXO.

As the frequencies don't match, I gues I can only use the device in single loop mode using PLL2.

At the moment I am able to get (correct) clocks at the output, using either of the inputs, but I cannot get the PLL2 DLD to assert.

On the board, the Status_LD2 is connected to an LED. by setting the output of the Status_LD2 pin to PLL2 DLD and output (push-Pull) or output inverted (push-pull) an can at least see that the pin works correctly.

For the configuration I am using TICS PRO. Two of my test configurations are attached.

Programming trhough spi is being done starting with

R0 (INIT)    0x000090 -> R0    0x000010

Then R1 through 357 (0x165) then R371 (0x173) then the rest of the registers as mentioned in the datasheet.

Any ideas?

LMK04832_settings_oscin.tcsLMK04832_settings.tcs

  • 0
    TI__Mastermind 33970 points

    Hi Bart,

    First, it is possible to use the PLL in dual-loop mode: 10 MHz and 122.88 MHz can be matched with a phase detector frequency of 80 kHz (10/125 = 122.88/1536).

    Second, I tested your configurations on an LMK04832EVM just now. I did get PLL2 DLD to activate for the 10 MHz input configuration, but only after setting PLL2 LD mode to push-pull. With the 122.88 MHz configuration, I suspect that the VCO frequency was just at the edge of the operating range, so unless the VCXO is being supplied with a voltage high enough to push the PLL2 VCO frequency above 2945 MHz, that configuration will not lock. Once the VCXO tuning voltage was set properly, I could lock this configuration as well.

    Double-check the PLL2 DLD polarity and output format, make sure the input slew rate on PLL1 is high enough, and make sure the VCXO is in range if used.

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 20 points

    Hi Derek,

    Thanks for the suggestions. The PLL2 DLD polarity being set to open drain in the config file was an error. I tested the design with the correct polarity.

    Right now I tested my board with the combination of PLL1 and 2 with the 80KHz phase detector frequency on pll1, I tested with 2 plls with an external clock of 12.288MHz and I retested 2 single loop combinations. None of them seem to lock..

    As I am not using an evaluation board, I have to manually program the IC through SPI. Are there any restrictions in writing the settings to the device? Do I use the exact order of registers being exported from TICS Pro? Are there any requirements on the time between writes?

    Anything else that can explain this?

  • 0 in reply to Bart Handels
    TI__Mastermind 33970 points

    Hi Bart,

    The datasheet provides the exact order in which the registers should be programmed, see section 8.5.1; TICS Pro should generate a programming file which conforms to the programming sequence requirements. It seems like you already have the right programming sequence from your initial post. I don't think this is a SPI issue.

    Is the slew rate on the input signal high enough? In the past, I have had issues with ~10 MHz sine wave input where the input power needed to be increased to meet the datasheet minimum input slew rate requirements. Differential sine wave slew rate is 2 * 2pi * f * Vpk = 0.126V/ns for 10 MHz input at +10dBm (1Vpk into 50Ω), compared to 0.15V/ns differential minimum for the datasheet. Using a sinusoidal single-ended signal generator, and a balun for differential conversion, I've sometimes had to go as high as +16dBm output power to get a stable lock.

    How were you confirming the output frequency correctness? You might want to double-check that the frequency is exactly correct, and not just very close. LMK04832 holdover or even a narrow pull range on PLL1 VCXO could produce a frequency which is close, but not exact. For example, I see <1PPM error on a frequency counter when the signal is truly locked and the 10MHz reference is unified between counter and signal generator. I see around 10PPM error when not locked.

    Regards,